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[pci] after synthesis
Hi,all
I'm using ISE4.1 to implement the pci core on a spartan2 150k
FPGA. After synthesis was done,when I launch the implementation
constraits editor,the following info appears:
Checking expanded design ...
WARNING:NgdBuild:526 - On the RAMB4_S16_S16 symbol
"bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2",
the
following properties are undefined: INIT_00, INIT_01, INIT_02,
INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A,
INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will
be
used.
WARNING:NgdBuild:452 - logical net
'bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/N_4' has no driver
WARNING:NgdBuild:454 - logical net
'bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/N_4' has no load
WARNING:NgdBuild:452 - logical net
'bridge/wishbone_slave_unit/fifos/wbw_fifo_ctrl/GND' has no driver
WARNING:NgdBuild:454 - logical net
'bridge/wishbone_slave_unit/fifos/wbw_fifo_ctrl/GND' has no load
WARNING:NgdBuild:452 - logical net
'bridge/wishbone_slave_unit/fifos/wbw_fifo_ctrl/VCC' has no driver
WARNING:NgdBuild:454 - logical net
'bridge/wishbone_slave_unit/fifos/wbw_fifo_ctrl/VCC' has no load
there are many of these warnings.
Could someone tell me something about this ? 3x
regards,
wangc
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