[openrisc] Cache Line Fill

[mphan@nimbuswireless.com]

Hi Damjan.

In the current design of orp_soc, with or1200_registered_ouput 
supported, a cache line fill takes 8 clocks (2-2-2-2) to fetch 4 DWORDs 
from the SRAM/FLASH. And a single  DWORD fetch takes 3 clocks 
(including one idle cycle of wb_cyc_o deasserted).

If we have a very fast internal SRAM, is it possible to do a cache line fill 
with 4/5 clocks (1/2-1-1-1) by changing the wb_stb logic in the 
or1200_wb_biu.v and do a single DWORD fetch with 2 clocks.

My next question is can we increase to cache size to 512 kB to reside 
the whole firmware and execute instructions from it with 0 wait state.  

Thanks

Michael Phan 
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