Re: [openrisc] Non-cacheable sectors

[lampret@opencores.org]

Heya !

For general understanding I want to make something clear. Cached and 
uncached areas should not be specified by architecture of the 
processor, but rather by system architecture. This is the reason why 
ORP as an example of reference system specifies what address space is 
cached and what not (usually cached is where peripherals are).

or1k architecture does specify that you can use MMU (via PTEs) to 
cache or uncache certain address spaces. However it doesn't specify 
how to cache/uncache address spaces if there is no MMU. Conclusion 
would be that implementation can chose its own way how to specify 
cached/uncached areas. For example if you look at or1200 you will see 
that if MMU is not impemented, you have a define that defines which 
areas will be cached and which not. See or1200_defines.v.

regards,
Damjan

----- Original Message ----- 
From: Marķa Bolado <mbolado@t... > 
To: "OpenRisc Forum" <openrisc@o... > 
Date: Wed, 20 Nov 2002 12:22:48 +0100 
Subject: [openrisc] Non-cacheable sectors 

> Hello again! 
> If you have an OR1000 implementation without virtual memory 
> (without MMU), how can you define non-cacheable memory sectors? 
> Aparently, the only way to define non-cacheable sectors is using 
> the PTEs, but if you don't use virtual memory, you don't have page 
> table. 
> 
--
To unsubscribe from openrisc mailing list please visit http://www.opencores.org/mailinglists.shtml