Re: [openrisc] ORPSOC clocking

["Damjan Lampret" <lampret@opencores.org>]

Heya !

All IP blocks run from the same clock, the WISHBONE clock. But some generate
internal clocks, like ssvga for example for the hsync and vsync. Look at the
RTL code for more info.

regards,
Damjan

----- Original Message -----
From: <ericbhyap@yahoo.com>
To: <openrisc@opencores.org>
Sent: Friday, January 03, 2003 2:47 AM
Subject: [openrisc] ORPSOC clocking


> Hi Damjan,
>
> I'm a little bit confused about the ORPSOC clocking relationship between
> the risc, ssvga, audio,ps2 , ethernet, flash, uart and other peripherals.
>
> In the rtl, it seems like all peripehral are running off on wb_clk which
is
> the same as clk, the risc clk.
>
> For example, vsync and hsync signals going to VGA displays, are they
> runniing in clk, or should they use the vga clk ?
>
> Can you show me a table what is the clocking frequency interface to the
> ORPSOC peripeheral ?
>
> How and where should I learn about this info ?
>
> Thanks.
>
>
> Eric
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