[openrisc] Re: 回信： [openrisc] Re: 回信： [openrisc] insn decoder and COFF loader

["Damjan Lampret" <lampret@opencores.org>]

> 1.)
> 1. fetch: h.2byteinsn  +  h.branch
> 2. fetch: h.2byteinsn + h.nop
>
> In this case we have a nop that will never be executed and is just taking
> code space.
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> Not really!!! Of course, our link register should point to the location
> of h.nop, so we don't need to worry about wasting code space.

But that means only 16-bit fetch accesses are naturally aligned. 32-bit
accesses are then non aligned and this requires extra fetch cycle. I thought
fetch is aligned to 32-bit in OR1601?

> since it will never be mixed together.
> ^^^^^^^^^ YES, we could let the 4byte insn named with prefix l.xxx if it
> helps us clarify this.

I think this would be great. I'll start changing mnemonics.

regards,
damjan