Re: [fpu] timing report

[Rudolf Usselmann <rudi@asics.ws>]

On Tuesday 30 April 2002 17:06, you wrote:
> Hi guys,
>
> I am using your Floating point core in my design.
>
> I am trying to use the code in my desin which I am implementing
> on a Xess 800 Virtex board.
>
> When I synthesize the module it tells me that i cannot clock at greater
> then 7 MHZ and
> I need my application to be running at 25 MHz atleast.
>
> The timing report says that the  Floating point core signals have a very
> high Fanout
> causeing negative slew.
>
> Please guide me as to what can be done to speed up the core.
>
> Regards
> Sumeet

The FPU was designed for standard cell and is not optimized for FPGAs.
It runs at about 200Mhz in UMC 0.18u.

You need a synthesis tool that has the "re-timing" option to get best 
results (e.g. Synopsys Design Compiler Ultra).

regards,
rudi
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