Re: [ethmac] reg-testbench module

["satya" <satya@iwavesystems.net>]

Hi Igor,

when I try to simulate the core,the core is perfectly working on PHY side but I m facing problems on Hoster Interface side.I am not using wishbone dam interface.so I commented the statement in defines file.But the data to the wishbone is  being fed like this:

once clock cycle some data and next xxxx and data and xxxx. I dont understand y u r doing like this.Please elaborate it if u dont mind.Awaiting for ur reply.

 

Thanks and regards

- satya

----- Original Message -----

From: Igor Mohor

To: ethmac@opencores.org

Sent: Saturday, February 09, 2002 4:01 PM

Subject: RE: [ethmac] reg-testbench module

What do you mean by not working properly? What errors do you get. I simulate with those files every day and it works

perfectly.

 

I would say that by not working you mean that there are no waves to see on the screen. I know that.

 

Open a wave wave window by yourself and then run the simulation after it's finished add signals to the wave window.

 

Do this sequence to do that:

 

First run the simulation and then type this (or add to the top_modelsim.do file)

view wave

add wave -r /*

restart -f

run -all

 

Regards,

    Igor

-----Original Message-----
From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On Behalf Of satya
Sent: 9. februar 2002 6:48
To: ethmac@opencores.org
Subject: [ethmac] reg-testbench module

Hi Igor,

the bench file you have given is not working properly when I try to simulate in Modelsim.Can you please help me in this regard?

awaiting for your reply.

 

Thanks and Regards

- satya