Re: [ecc] Reed Solomon decoder

[Duane Clark <dclark@akamail.com>]

inada@singnet.com.sg wrote:
> Hi,
> I'm implementing Reed Solomon (255,223) on FPGA using VHDL. I've 
> implemented a RS(15,11) as a prototype and it works fine. however, i 
> faced trouble when i try upscale it to (255,223) which used up a huge 
> number of gates and slices. I believe this is mainly due to the finite field 
> conversion(exponential to binary) table implemented in the code. Is 
> there any way shorter/more effective way of implementating the finite 
> field conversion? other ideas on the code are welcomed!!! Please help!!

I have a Reed Solomon (255,223) decoder running in an XCV600 FPGA. I did 
not use any exponential/binary or binary/exponential lookup tables. 
Instead, I generated fixed GF multipliers directly, and just used a lot 
of them. Implemented in XOR gates, the GF multiplier is just 8 multiple 
input XOR gates.

Of course, every multiplier is different, depending on the fixed alpha 
that the input is being multiplied by. I generate those with a C code 
algorithm that generates the output directly in VHDL format, which I 
then pipe into a package file.

An additional big advantage of using a method such as this is that it is 
extremely fast. I did not bother to floorplan, and the decoder will run 
at 70MBytes per second.

Because I had a bunch of spare block RAMs available, I implemented some 
of the multipliers in lookup tables. This freed up some LUTs to be used 
elsewhere. Again, this is hardcoded GF multipliers, and not 
exponential/binary tables. A 256x16 block ROM can implement 16 
multiplier bits.

I used the same method of using C code to generate the contents of the ROM.



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