[ecc] RE:

[Phil Chien <phil@mosart.com.tw>]

hi there,

I don't know where you see the sentence. But if you want to 
generate a pure 64KHz ( I mean either rising or falling edge
are correct), it's impossible by digital way.

I think "gapping" is just  "mask 1 cycle from 9 cycles" to achieve
a non-ideal 64KHz.

Anyone has better idea?

regards,
Phil

-----Original Message-----
From: zhu.xiangyang@mail.zte.com.cn
[mailto:zhu.xiangyang@mail.zte.com.cn]
Sent: Tuesday, December 05, 2000 8:37 AM
To: ecc@opencores.org
Subject: 




'A 64KHZ clock is generated by gapping a 72KHZ clock'.
How to gapping a clock?  Can it be done by verilog/VHDL?