Re: [oc] VHDL Help...

[Shehryar Shaheen <shehryar.shaheen@ul.ie>]

Try this

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.MATH_REAL.ALL;                   <-- Add this package

ENTITY mux IS
GENERIC( size_data : integer := 8 );
PORT(
           data : IN STD_LOGIC_VECTOR(size_data-1 downto 0);
           sel  : IN STD_LOGIC_VECTOR( integer(ceil(log2(real(size_data))))
downto 0);   <-- Put this line in place
           result : OUT STD_LOGIC
        );
END mux;

This should work if your compiler is VHDL93 compliant
in case you are using modelsim complie it with these switches

vcom -93 -explicit
on the 'sel' line type conversion is necessary since VHDL is fussy about
types.

Hope this Helps

Regards

Shehryar

----- Original Message -----
From: "Héctor Orón Martínez" <hecormar@teleco.upv.es>
To: <cores@opencores.org>
Sent: Monday, May 26, 2003 12:06 PM
Subject: [oc] VHDL Help...


Dear cores,

     Well, my problem is that writing an entity i have to use two
     variables, but i think it is a way to write it with one variable,
     i don't know if this line is correct, but compiler tells me it
     isn't... do you think that i could do it this way ?

     PROBLEM ON: (ceil(log2(tamany_data)))

     --< CODE > ---------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY mux IS
GENERIC( size_data : integer := 8 );
PORT(
           data : IN STD_LOGIC_VECTOR(size_data-1 downto 0);
      **   sel     : IN STD_LOGIC_VECTOR(ceil(log2(size_data)) downto 0); **
           result : OUT STD_LOGIC
        );
END mux;

    --< END CODE >----------------------------------------------------


--
Cheers,
 Héctor                          mailto:hecormar@opencores.org

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