Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

[Rudolf Usselmann <rudi@asics.ws>]

On Wed, 2003-05-21 at 22:32, Marco Antonio Simon Dal Poz wrote:
> 
> Thanks for the info. As a matter of fact, when I started in ASIC design,
> DC was already available, so I never tried previous tools.
> Anyway, Synopsys is dominant for historical reasons, but nowadays is it
> still the best tool for ASIC design?

I can't tell you if it is the "best" tool or not. I know there
are a lot of good synthesis tools out there for ASICs and Design
Compiler is one of them. So far I think synopsys was able to keep
up with all the new hot startups with really nifty tools, like
Magma for example. I think quite a few of them are good. My guess
is if you ask 10 engineers which is the better tool, you might
get 10 different answers !

> I think that FPGA Express had done a great job, but didn't evolve as
> others specific FPGA tools did. As there is a trend of junction of several
> tools in one big packet (e.g. Cadence has tools of IC layout, HDL
> sinthesis and even PCB schematic and layout!) for entire system design,
> there should be interest from Synopsys in FPGA, just for tool
> completion. For the user, it is interesting that only one tool could do
> all the job (including FPGA prototyping) because it is common that FPGA
> specific tools (from FPGA vendors) just support a subset of the HDL used
> (as Xilinx and Altera always did).

Yes, I too would have loved to see an alternative to the Xilinx &
Altera P&R tools. It would indeed be nice to have one entire solution
from a commercial vendor that will go from synthesis to P&R to
bit stream generation.

However, we must not forget the driving force in the FPGA market: cost.
ASIC tools like Design Compiler can easily cost you $100K (USD) per
year. Add back-end tools and a few verification tools and we are
easily talking about $250-$500K USD per year for tools.

Most people who are using FPGAs, don't want to spend the $2K (?) for
the full version of the Xilinx tools that are commercially available.
They prefer to use the Web-pack ! Makes me laugh each time I see them
complaining how shitty the web-pack is ! You see these two markets
have been always separated by a big cost difference. FPGA guys want
everything free, ASIC guys are used to spend 6 digit sums on tools.

So thats why we do not see complete solutions there at all. Nobody
wants to invest the money and time to develop a nice P&R tools that
none will buy. Thats why Synopsys isn't paying to much attention to
their FPGA tools. They are probably loosing money in developing and
supporting them. The only reason they don't drop them is to provide
a solution for their ASIC customers who are interested.

People like Synplify and Leonardo, have formed a nice niche for them
selfs in FPGA synthesis.

> I think you misunderstood me. I didn't say VHDL is better, I just would
> like to know why Verilog was choosen. As you also prefer Verilog, I would
> like to listen to your opinion.

I use verilog because 99.5% of my customers ask for verilog
support/solutions. I bought VHDL books twice to learn VHDL,
ended up throwing/giving both away, never learning VHDL. :*(

Regards, 
rudi               
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