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Verilog vs VHDL (Was: Re: [oc] Verilog coding style...)
Aloha!
paul wrote:
> Allow a student to inject some comments. I was taugh PASCAL in grade 11,
> and Modula-2 in freshman year, but the world is using C.
> I really don't want to end up learning "PASCAL" or "modula-2" (VHDL)
> while I must use C (verilog) in work....
> Or the converse....
Congratulations! Not many have learned Modula-2, or Modula-3 for that matter.
They are excellent tools to learn encapsulation, modular design, abstract data
types, object orientation and writing clean interfaces with methods without
side effects. With that as a background you are well prepared to work with
things like IP-cores för SoC design.
Bring the mind set, apply using a new tool (language). In this vase Verilog.
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Med vänlig hälsning, Yours
Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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