Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

[Rudolf Usselmann <rudi@asics.ws>]

On Tue, 2003-05-20 at 23:28, Marco Antonio Simon Dal Poz wrote:
> On Tue, 20 May 2003, [ISO-8859-1] Joachim Strömbergson wrote:
> 
> > > AFAIK, the industry is trying to steer in the direction of discarding
> > > Synopsys. Please, correct me if I am wrong...
> > 
> > <rant>
> > You are wrong. ;-)
> 
> Ok, I forgot to tell I was talking about FPGAs. I hadn't imagine that ASIC
> market was that different from FPGA market.

Gee, minor oversight I guess ...

> > There are specific areas where Cadence, Mentor et al are big and
> > dominate, but for large parts of the ASIC design flow, Synopsys not
> > only dominate but have gained market share. This has both to do with
> > the (so far) successful merger with Avanti, but old Synopsys tools
> > have in same cases increased market share (where it is possible - for
> > STA PrimeTime is basically alone anyways).
> 
> What is the big deal with Synopsys tools that it has been chosen as THE
> tools and not Cadence and MG tools?
> 
> > If you don't trust me, please check John Cooleys trip reports for the latest 
> > DAC and SNUG [1]. Yes, SNUG is a Synopsys event, but you can probably trust 
> > your fellow engineers when it comes to the tool polls.
> 
> Thanks for the URLs. But Synopsys leadership is not too far away from
> Cadence.

Synopsys was one of the first companies to write a decent
synthesis tool. Before there was design compiler, all we
had where the Berkley tools. And I can tell you, it was a
pain in the neck.
When Synopsys released the first DC, it was like a new
millennium in chip design has begone. And it did.

The only reason Synopsys tried to get in to the FPGA market
was because there was only the usual crap available from the
FPGA vendors. Synopsys customers (many use FPGAs for prototyping),
have asked them to support FPGAs. Synopsys is/has never been
interested in this market, but was mostly doing it a a favor
to it's customers. When Synplify and Leonrdo came along, they
where doing a much better job on FPGAs because that was thei
main business.

> I am used to do FPGA hardware design with Verilog and VHDL, and I can't
> see why Verilog is so better than VHDL. In fact, I see advantages and
> disadvantages in both sides, so, why Verilog is still dominant?

I guess everybody forgot to ask you !

Just send an email to Sun, CISCO, 3com, Motorola, TI, etc., etc.
and tell them how stupid they all are for using Verilog and how
VHDL is much better !

> Best wishes,
> 
> Marco Antonio

Regards, 
rudi               
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