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Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1

To: cores@opencores.org
Subject: Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
From: Niclas Hedhman <niclas@hedhman.org>
Date: Sat, 17 May 2003 15:59:58 -0800
In-Reply-To: <006101c31c1e$c88a2880$ef01ed0a@flextronics.si>
Organization: Bali Automation Sdn Bhd
References: <3EC510C6.2090801@InformAsic.com> <006101c31c1e$c88a2880$ef01ed0a@flextronics.si>
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On Friday 16 May 2003 06:47 pm, Damjan Lampret wrote:
> There is a document that tries to address exactly this issue. It is called
> OpenCores Coding Guidelines. 

And it is not that hard to put together a piece of software that re-formats 
the code to a coding style, which one runs before submitting it into the CVS. 
(Note, NO GOOD to constantly changing style, as CVS will think it is a 
modification, and history of changes gets lost in the styling noise.)

Niclas
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References:
- [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
  - From: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
- Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
  - From: "Damjan Lampret" <lampret@opencores.org>

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