Re: [oc] Video Timing generator(RS170) interlaced in VHDL help

[John Kent <jekent@optushome.com.au>]

http://www.cs.ubc.ca/spider/jennings/vid_sw/article.pdf

Its a video switch, with some VHDL code ...
I entered "RS170" and "VHDL" into a google search and it turned up this 
document ....

It may or may not help you.

John.

edwinstuff@yahoo.com wrote:

>I'm currently working on the Video Timing generator(RS170) in VHDL and 
>have problem on the interlaced mode.
>
>I know how the non-interlaced mode work but I couldn't get the 
>interlaced mode to work.  
> 
>As I know, even scanning will have half of clock cycle earlier than odd
>scanning on the front porch. Is that it?  what else I have to consider?  
>The Video board still doesn't recognized it's a interlaced mode all the 
>time.
>
>Tried to find information about it but couldn't find it.  Any help is greatly 
>appreciated. thanks
>
>edwinstuff@yahoo.com
>--
>To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml
>
>  
>

-- 
http://members.optushome.com.au/jekent



--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml