Re: [oc] T80 cpu version 0242 released

["MikeJ" <mikej@freeuk.com>]

Hi,

It is a right pain to use a mixture of positive and negative edge clocking,
so if possible use a clock that is twice the frequency instead. The T80 core
bus timing has been simplified for this reason, but if you need 2 clock r/w
cycles then have a look at the T80 core in the Pacman code which uses the
t80sed (synchronous, clock enable, double cycle) module to do this.

Cheers,
MikeJ

> >
> > Thanks to MikeJ the instruction timing has been verified against a
> > real
> > Z80 and they now stay in sync indefinitely when they are compared
> > in
> > Mike's pacman implementation.
> >
>
> Greetings,
>
> I have been playing around a bit with trying to get the *bus* timing
> consistent with the Z80 documentation.  There is a whole bunch of
> things happening on the downclocks, and my main goal with this was to
> try to re-establish the Z80 bus condition that you have at least 1.5
> cycles (for M1, 2.0 cycles for the rest) from MREQ# asserted until
> data is due, whereas the T80s implementation only gives you 1.0 cycles.
>
> This is taken straight from the timing diagrams of the Z80 bus, as
> currently published by Zilog:
>
> http://www.zilog.com/docs/z80/um0080.pdf (pages 11-21).
>
> What's not clear to me is how this affects the timing within the core
> (the T80 module, as opposed to the T80s module.)  In particular,
> memory read data is now latched in the middle of T3, as opposed to at
> the end of T2.  I'm not sure I'm doing that particular aspect right;
> I'm currently trying to set up a simulation test bench that's accurate
> enough to test this, the current one I have isn't all that accurate...
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