Re: [oc] Regarding the low power bus encoding research ?

[nico <nicolas.boulay@ifrance.com>]

Before regarding switching activity, you must think about clock gating
of the register use for the bus. Clock tree are 70% of the power
consumption of a chip. 

If you think of register configuration each little
flip-flop receive the clock, you could have hundred of them. But
such registers only need the clock in writing. And configuration write
are very uncommon. So write signal should be used to mask/unmask the
clock of such register bank.

Maybe an other way could be investigate : enable the clock of the module
the time to process a bus request. When playing with the clock, you
could have some chicken&eggs problem. It's easy to shut up the clock,
but impossible to reneable it without external help.

Maybe the bus could provide a clock enable signal. And a system could
let run the clock 16 or more cycles after this signal goes low (the
slave IP are wake up by external access but shut it-self down).

nicO

On Wed, 27 Nov 2002 09:24:14 +0800
NansonHuang@itri.org.tw wrote:

> 
>  Hi,
> 
>  I am now surveying the papers how to achieve the on-chip low power
>  bus.
> Most of them are focus on decorrelating/encoding the bus data to
> reduce the switching activity. There are a lot of work on it. However,
> I am not sure if there are any
> commerical on-chip bus standard SoC product(Wishbone, AMBA, Sonic.etc)
> utilizing
> the low power encoding scheme. In others words, does it work to lower
> the power consumption in SoC ? Coud anyone give me some ideas to let
> me know if I will go on further ?
> 
>  All the best,
> 
>  Nanson
> 
> 
> 
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