Re: [oc] vhdl code for SPI master slave core

[Simon Srot <simons@opencores.org>]

Hi,

There is a project on http://www.opencores.org/projects/spi/ , but it is
only master core and written in verilog.

Simon

ai9824@wayne.edu wrote:
> 
> hai ,
> 
> Iam looking a vhdl code for serial peripheral interface master slave core
> and its testbench with bit rates generated in master mode as
> 
> 2, 4, 8,16,128,256
> 
> if any body have this code please help me
> 
> have a nice day
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