[oc] vhdl top level help

[ckh827@hotmail.com]

what is the correct way to write top level vhdl file?
on each separate files, I used package and component. but it only work
for bit and not for std_logic(it says it can't be defined).  Any one
of you has an idea how to combine all files correctly?

For example,in one of the macro,
--****************************************************
package backlightI2C_pkg is
component backlightI2C
	port (  sda : inout std_logic;
           scl : in std_logic;
			  clk : in std_logic;
       dataout : out std_logic_vector(7 downto 0));
	end component;
end backlightI2C_pkg;

entity backlightI2C is
   Port (  sda : inout std_logic:= 'Z';
           scl : in std_logic;
			
			  clk : in std_logic);
	   	dataout : out std_logic_vector(7 downto 0));
end backlightI2C;
--****************************************************
for top level program,
--****************************************************

library ieee;
use ieee.std_logic_1164.all;
use work.backlightI2C_pkg.all;
entity toplevel is port (
......
......
......
--****************************************************






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