RE: [oc] I2C noise filtering

[Illan Glasner <IGlasner@mrv.com>]

Hi,

   You can try something like :

reg     [2:0]   scnt; 
always @(posedge pi_clk or negedge rstn) 
if (~rstn) 
   scnt <= #1 0;
else if (scl)
   scnt <= #1 (scnt==7) ? 7 : scnt + 1 ; 
else
   scnt <= #1 (scnt==0) ? 0 : scnt - 1 ; 

reg     po_scl_cln   ;
always @(posedge pi_clk) 
if (~rstn) 
   po_scl_cln <= #1 0;
else 
   po_scl_cln <= #1 scnt[2] ;


keep in mind that if you use Xilinx you probably will need to send
po_scl_cln to a general IO make an external connection on the board to GCLK
IO in order to use the clock resource.

if you are using altera in this matter it should be easier as you can use
directly the po_scl_cln.

where pi_clk is a high frequncy clock much faster than the scl something
like 10M.

if you don;t have high frequnacy you can make another "loop" of geenral IO
to GCLK input and simple generate internaly a free runing ring osc using let
say 6 buffer and invertor and this should do the job.

have a nice day

   Illan



-----Original Message-----
From: ckh827@hotmail.com [mailto:ckh827@hotmail.com]
Sent: Wednesday, November 06, 2002 8:01 PM
To: cores@opencores.org
Subject: [oc] I2C noise filtering




When I try to synthesize the I2C verilog from Richard (Opencores), It 
said unable to open timescale.v. But I already added the source in the 
project.  Anybody has any idea?

And also, how can I filter out the noise from scl and sda lines?

I'm urgently need a working I2C slave model because I already worked 
for more than 3 weeks but still not able to ping correctly.

Any help is appreciated.

Ken
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