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Re: [oc] sdram controller and clock issues
no , i think i am not using the one written by you, but would certainly like to
know how it is done . Could you please send me the link to where I can find the
controller written by you.
thanks in advance,
vimal
--- Rudolf Usselmann <rudi@asics.ws> wrote:
>
> There are several SDRAM controller available on OpenCores.
>
> IF you are using the one I have written, read the manual. It clearly
> states how to clock the controller and the SDRAM.
>
> rudi
>
> On Tuesday 16 April 2002 07:29 pm, you wrote:
> > I was trying to use the SDRAM controller at open cores
> > with the Micron SDRAM MT48LC2M32B2 . The verilog model
> > for the SDRAm has the follwoing setup and hold
> > violatoins defined. So if I use the same clock for the
> > controller and the SDRAM I get setuphold violations
> > because when I issue a command from the controller it
> > violates the setup and hold times on the SDRAM model.
> > So what should be the clock that goes to the
> > controller
> > and the SDRAM . I mean, what is the general
> > practice.how should their phases be natched and how
> > would one recommend it be implemented.
> > $setuphold(posedge Clk, Cke, tCKS,
> > tCKH);
> > $setuphold(posedge Clk, Cs_n, tCMS,
> > tCMH);
> > $setuphold(posedge Clk, Cas_n, tCMS,
> > tCMH);
> > $setuphold(posedge Clk, Ras_n, tCMS,
> > tCMH);
> > $setuphold(posedge Clk, We_n, tCMS,
> > tCMH);
> > $setuphold(posedge Clk, Addr, tAS,
> > tAH);
> > $setuphold(posedge Clk, Ba, tAS,
> > tAH);
> > $setuphold(posedge Clk, Dqm, tCMS,
> > tCMH);
> > $setuphold(posedge Dq_chk, Dq, tDS,
> > tDH);
> >
> > thanks,
> > vimal
> >
> >
> >
> > =====
> > Vimal Reddy
> > Graduate Student
> > Computer Engineering
> > North Carolina State University
> > Raleigh, NC
> > Ph: (919) 859 5920
> >
> > __________________________________________________
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>
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=====
Vimal Reddy
Graduate Student
Computer Engineering
North Carolina State University
Raleigh, NC
Ph: (919) 859 5920
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