[oc] WISHBONE ack_o signal imlpementation

[Jacob Gorban <jacob.gorban@flextronicsdesign.co.il>]

I have a question about imlpementing WISHBONE's ack_o signal in verilog.

I have the following need:
1. One wait state (ack_o) is returned one clock after stb_i and cyc_i 
are asserted.
2. The ack_o should be asserted for one clock only and go down when 
stb_i goes down (required by WISHBONE spec).
3. It should not toggle in long cycles.

There are no other clocks except the wishbone bus clock.


The simplest imlpentation:
1) 
wb_ack_o <= #1 wb_cyc_i & wb_stb_i;
does one clock delay but it also delays the deassertion of wb_ack_o for 
one clock too.

So, the following seemed like a good idea:
2) 
wb_ack_o <= #1 wb_cyc_i & wb_stb_i & !wb_ack_o;
It was ok until David C.Davies pointed me out that on long cycles 
(longer than 1 or 2 clock cycles) it toggles.

Looking at the WISHBONE spec I found that WISHBONE master should 
deassert its cyc_o and stb_o next clock after receiving ack_i. That way 
David's description of long cycles seems to be violating the rules of 
WISHBONE.

In that case the second implementation seems to be the right one.

Am I right on this?


-- 
Jacob Gorban
Flextronics Semiconductor
T: +972-54-656775
F: +972-8-9275552
1 Lev Pesah st,
North Industrial Zone, 71293, Lod
Israel

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