Mail Index
Thread Index
Re: [oc] I2C Core, SPI Core
From
: golden_1@126.com
[oc] I2C VHDL module
From
: Edi <edi_f@sancastle.com>
Re: [oc] A 'core server' ?
From
: "Marko Mlinar" <markom@opencores.org>
[oc] Rave News & Party Listings from the Loop
From
: The Loop Newsletter <karmaloop2@roving.com>
Re: [oc] fastest fft
From
: "rohit kumar" <rohitkumar_1@lycos.com>
Re: [oc] file organization
From
: John Dalton <john.dalton@bigfoot.com>
Re: [oc] A 'core server' ?
From
: Tomas Bautista <bautista@cma.ulpgc.es>
[oc] Re: more inf. bout firewire
From
: "Johnsonw10" <johnsonw10@hotmail.com>
Re: [oc] A 'core server' ?
From
: "Johnsonw10" <johnsonw10@hotmail.com>
Re: [oc] A 'core server' ?
From
: Jecel Assumpcao Jr <jecel@merlintec.com>
Re: [oc] A 'core server' ?
From
: John Dalton <john.dalton@bigfoot.com>
Re: [oc] A 'core server' ?
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] file organization
From
: "Damjan Lampret" <lampret@opencores.org>
Re: [oc] fastest fft
From
: someone@somewhere.com
Re: [oc] GPIO core
From
: "Damjan Lampret" <lampret@opencores.org>
Re: [oc] A 'core server' ?
From
: "Marko Mlinar" <markom@opencores.org>
[oc] GPIO core
From
: Richard Herveille <richard@asics.ws>
Re: [oc] A 'core server' ?
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] A 'core server' ?
From
: "Marko Mlinar" <markom@opencores.org>
Re: [oc] file organization
From
: John Dalton <john.dalton@bigfoot.com>
Re: [oc] file organization
From
: Rudolf Usselmann <rudi@asics.ws>
[oc] A 'core server' ?
From
: John Dalton <john.dalton@bigfoot.com>
Re: [oc] 8051 VHDL models search
From
: shipinghe@hotmail.com
RE: [oc] CRC cores
From
: "Erwin Sutanto" <erwin_sut@hotmail.com>
Re: Re: [oc] Regarding - 8051 c0re specification
From
: mlampret@opencores.org
Re: [oc] file organization
From
: "Damjan Lampret" <lampret@opencores.org>
Re: Re: [oc]:Help on DESIGN 0F INTEL 8051 CORE DESIGN IN VERILOG
From
: "ramesh s" <ramesheie@rediffmail.com>
Re: Re: [oc]:Help on Backend Verification
From
: "ramesh s" <ramesheie@rediffmail.com>
Re: Re: [oc] Regarding - 8051 c0re specification
From
: "ramesh s" <ramesheie@rediffmail.com>
[oc] file organization
From
: "llbutcher" <llbutcher@veriomail.com>
[oc]:Help on Backend Verification
From
: khong lin pang <mailtopang@yahoo.com>
Re: Re: [oc] RS-232 <-> PS/2
From
: "Kevin L. Neff" <NeffK@uwplatt.edu>
[oc] New OC web
From
: Miha Lampret <mlampret@opencores.org>
Re: [oc] RS-232 <-> PS/2
From
: "Branko badrljica" <brankob@avtomatika.com>
[oc] RS-232 <-> PS/2
From
: "studio tibor" <tibor@siol.net>
RE: [oc] CRC cores
From
: "Bobko, Paul" <Paul.Bobko@marconi.com>
[oc] CRC cores
From
: "Erwin Sutanto" <erwin_sut@hotmail.com>
Re: [oc]:Help on Backend Verification
From
: naveena.padmaraju@wipro.com
Re: [oc]:Help on Backend Verification
From
: Rudolf Usselmann <rudi@asics.ws>
Re: [oc] Regarding - 8051 c0re specification
From
: Miha Lampret <mlampret@opencores.org>
[oc] Regarding - 8051 c0re specification
From
: "ramesh s" <ramesheie@rediffmail.com>
[oc] Demand for one core
From
: monhi@ce.sharif.edu
[oc]:Help on Backend Verification
From
: khong lin pang <mailtopang@yahoo.com>
[oc] opencores coding guidelines
From
: "Damjan Lampret" <lampret@opencores.org>
[oc] new I2C Documentation release
From
: Richard Herveille <richard@asics.ws>
Re: [oc] looking for work
From
: "Damjan Lampret" <lampret@opencores.org>
[oc] looking for work
From
: "bhupesh ramchandani" <bhupesh_r@rediffmail.com>
[oc] NEW: WISHBONE Interconnect Matrix
From
: Rudolf Usselmann <rudi@asics.ws>
[oc] WISHBONE DMA/Bridge IP Core Update
From
: Rudolf Usselmann <rudi@asics.ws>
[oc] (sans sujet)
From
: XGuillot@aol.com
[oc] Self assembly in transistor fabrication (correction)
From
: johnd@southern-poro.com
[oc] Self assembly in transistor fabrication
From
: jdalton@asiaonline.net.au
[oc] Core updates: I2C, OCIDEC-1, VGA/LCD
From
: Richard Herveille <richard@asics.ws>
[oc] Official Wishbone rev.B2 specs available
From
: Richard Herveille <richard@asics.ws>
Re: [oc] 8051 VHDL models search
From
: Philipp Krause <pkk@spth.de>
[oc] 8051 VHDL models search
From
: Jean Masson <Jean.Masson@lium.univ-lemans.fr>
[oc] subscribe jeks@sverige.nu
From
: "kwak" <jeks@sverige.nu>
[oc] Simulating Synthesised VHDL files using Synopsis
From
: rmmy@ee.iitb.ac.in
[oc] DES Core
From
: Rudolf Usselmann <rudi@asics.ws>
[oc] 82C42 PS2 keyboard controller core
From
: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Re: [oc] CRC calculation.
From
: "Naveena Padmaraju" <naveena.padmaraju@wipro.com>
Re: [oc] How to submit
From
: Miha Lampret <mlampret@opencores.org>
Re: [oc] Xilinx block-RAM async read
From
: "Andras Tantos" <andras_tantos@yahoo.com>
Re: [oc] wide crc_32 doesn't need to be slow.
From
: Allan Herriman <allan_herriman.hates.spam@agilent.com>
Re: [oc] Xilinx block-RAM async read
From
: Richard Herveille <richard@asics.ws>
Re: [oc] New project proposal
From
: "Damjan Lampret" <lampret@opencores.org>
Re: [oc] Xilinx block-RAM async read
From
: Damjan Lampret <lampret@opencores.org>
[oc] New project proposal
From
: "Andras Tantos" <andras_tantos@yahoo.com>
[oc] Xilinx block-RAM async read
From
: "Andras Tantos" <andras_tantos@yahoo.com>
[oc] wide crc_32 doesn't need to be slow.
From
: "llbutcher" <llbutcher@veriomail.com>
[oc] How to submit
From
: 98019 Irawan Budhi A <irawan@students.ee.itb.ac.id>
Re: [oc] DES question
From
: Rudolf Usselmann <rudi@asics.ws>
[oc] Request doc.
From
: XGuillot@aol.com
[oc] DES question
From
: "Mark Cynar" <mcynar@jta.com>
[oc] CRC Calculation
From
: naveena.padmaraju@wirpo.com
Re: [oc] CRC calculation.
From
: "Paul Baxter" <paul_baxter@ntlworld.com>
Re: [oc] CRC calculation.
From
: Allan Herriman <allan_herriman.hates.spam@agilent.com>
Re: [oc] CRC calculation.
From
: "llbutcher" <llbutcher@veriomail.com>
Mail converted by
MHonArc
2.4.4