[oc] Memory Controller Update

[Rudolf Usselmann <rudi@asics.ws>]

I checked in a new version of the memory controller. The changes are:


1) Fixed Chip Select Mask
   -  Reset Value is now all ones
   -  Masking logic was incorrect as well, I fixed it.

2) All resets are now really async

3) During Reset all outputs are forced Hi-Z

4) Chip Select output Registers are now initialized to '1' after reset.


I also Added some configurable items (need to update the spec).
Here is a brief description:


POR_DELAY

If defined, the memory controller will stall after a reset for
POR_DELAEY_VAL of nS/uS.



POR_DELAEY_VAL

A 8 bit value, specifying how many memory clock cycles to wait
after power on reset before allowing access to the memory bus.
(For a 100 Mhz mem_clk, a value of 250 would mean 2.5 uS).


rudi