Re: [oc] Verilog Preprocessor

[Lawrence Butcher <Lawrence.Butcher@Sun.COM>]

First, I am sorry to have sent this to the whole group.

I will try to be more careful in the future.

Second, I am sorry for the typo.  I ment that the
preprocessor should be available in 2 CLICKS from where
the verilog is, in the sense of web links.

Sorry Sorry.

Lawrence

> X-Authentication-Warning: iza.mr2.si: majordom set sender to 
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> Date: Wed, 9 May 2001 19:18:27 -0700 (PDT)
> From: Lawrence Butcher <Lawrence.Butcher@Sun.COM>
> Subject: Re: [oc] Verilog Preprocessor
> To: cores@opencores.org
> MIME-Version: 1.0
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> 
> Dont.  DONT!
> 
> That way, your code will only be usable wherever the preprocessor is.
> 
> I am a big fan of straight Verilog (no PLI, no pre-processor).
> 
> Unless the pre-processor is available by at most 2 clocks
> from where the Verilog is!
> 
> Lawrence
> 
> 
> > X-Authentication-Warning: iza.mr2.si: majordom set sender to 
> owner-cores@opencores.org using -f
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> > Date: Thu, 10 May 2001 08:48:33 +0700
> > Subject: [oc] Verilog Preprocessor
> > From: Rudolf Usselmann <rudi@asics.ws>
> > To: OPENCORES <cores@opencores.org>
> > Mime-version: 1.0
> > Content-transfer-encoding: 7bit
> > 
> > 
> > Anybody knows where I can get a Verilog Preprocessor ?
> > Something similar to cpp or even m4, but for verilog systnax.
> > 
> > Thanks,
> > -- 
> > rudi
> > 
> > 
>