[oc] ATM Core

[Rudolf Usselmann <rudi@inet.co.th>]

Hi guys !

I can design the ATM core if there is interest.

I am already famillilar with the PHY interface (UTOPIA 3), what kind of an
interface would you like to see on the other side ? I guess a DMA type of
general i/f ? Did you guys try to define an internal i/f spec for various
blocks so they could all talk to each other without to much glue ?

One thing that should go along with the ATM Core is PHY Config I/F core.

Cheers,
rudi

PS: using VCS verilog ...