head	1.2;
access;
symbols
	rel_1_1:1.2
	rel_1_0:1.2
	rel_0_6_1_beta:1.2
	rel_0_6__beta:1.2
	rel_0_6_beta:1.2
	rel_0_5_beta:1.2
	rel_0_4_beta:1.2
	rel_0_3_beta:1.2
	rel_0_2_beta:1.2
	rel_0_1_beta:1.2;
locks; strict;
comment	@# @;


1.2
date	2004.04.18.19.01.56;	author arniml;	state Exp;
branches;
next	1.1;

1.1
date	2004.04.09.19.15.59;	author arniml;	state Exp;
branches;
next	;


desc
@@


1.2
log
@fix name of istrobe
@
text
@.t48_core_b.decoder_b.istrobe_q
.t48_core_b.pmem_ctrl_b.program_counter_q[11:0]
.t48_core_b.alu_b.accumulator_q[7:0]
.t48_core_b.psw_b.sp_q[2:0]
.t48_core_b.psw_b.psw_s[7:0]
.t48_core_b.use_db_bus.db_bus_b.bus_q[7:0]
.t48_core_b.decoder_b.f1_q
.t48_core_b.use_p1.p1_b.p1_q[7:0]
.t48_core_b.use_p2.p2_b.p2_q[7:0]
.t48_core_b.decoder_b.mb_q
.ram_256.ram_b.data_tmp[7:0]
.ram_256.ram_b.address_tmp[7:0]
.ram_256.ram_b.we_tmp
@


1.1
log
@initial check-in
@
text
@d1 1
a1 1
.t48_core_b.decoder_b.istrobe_s
@