head     1.1;
branch   1.1.1;
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symbols  INITIAL:1.1.1.1 ARIF_E_NUGROHO:1.1.1;
locks    ; strict;
comment  @# @;


1.1
date     2005.12.06.02.48.32;  author arif_endro;  state Exp;
branches 1.1.1.1;
next     ;
commitid        4fe74394fbb84567;

1.1.1.1
date     2005.12.06.02.48.32;  author arif_endro;  state Exp;
branches ;
next     ;
commitid        4fe74394fbb84567;


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1.1
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@Initial revision
@
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@-- $Id: counter2bit.vhdl,v 1.4 2005/12/03 23:43:14 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title       : Counter 2 bit
-- Project     : Mini AES 128 
-------------------------------------------------------------------------------
-- File        : counter2bit.vhdl
-- Author      : "Arif E. Nugroho" <arif_endro@@yahoo.com>
-- Created     : 2005/12/03
-- Last update : 
-- Simulators  : ModelSim SE PLUS 6.0
-- Synthesizers: ISE Xilinx 6.3i
-- Target      : 
-------------------------------------------------------------------------------
-- Description : Counter 2 bit (e.g. from 0 to 3)
-------------------------------------------------------------------------------
-- Copyright (C) 2005 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- 
--         THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
-- 
-------------------------------------------------------------------------------
-- 
--         THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- 
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter2bit is
   port (
      clock : in  std_logic;
      clear : in  std_logic;
      count : out std_logic_vector (1 downto 0)
      );
end counter2bit;

architecture data_flow of counter2bit is
signal tmp : std_logic_vector (1 downto 0) := ( B"00" );
begin
   process (clock, clear)
   begin
      if (clear = '1') then
         tmp <= "00";
      elsif (clock = '1' and clock'event) then
         tmp <= tmp + 1;
      end if;
   end process;
   count <= tmp;
end data_flow;
@


1.1.1.1
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@Initial Checkin.
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