head	1.2;
access;
symbols;
locks; strict;
comment	@# @;


1.2
date	2001.08.10.08.16.21;	author rudi;	state Exp;
branches;
next	1.1;

1.1
date	2001.07.29.07.34.41;	author rudi;	state Exp;
branches;
next	;


desc
@@


1.2
log
@
- Changed IO names to be more clear.
- Uniquifyed define names to be core specific.
- Removed "Refresh Early" configuration
@
text
@
all:	sim
SHELL = /bin/sh
MS="-s"

##########################################################################
#
# DUT Sources
#
##########################################################################
DUT_SRC_DIR=../../../rtl/verilog
_TARGETS_=	$(DUT_SRC_DIR)/mc_top.v			\
		$(DUT_SRC_DIR)/mc_wb_if.v		\
		$(DUT_SRC_DIR)/mc_cs_rf.v		\
		$(DUT_SRC_DIR)/mc_rf.v			\
		$(DUT_SRC_DIR)/mc_adr_sel.v		\
		$(DUT_SRC_DIR)/mc_dp.v			\
		$(DUT_SRC_DIR)/mc_rd_fifo.v		\
		$(DUT_SRC_DIR)/mc_refresh.v		\
		$(DUT_SRC_DIR)/mc_obct.v		\
		$(DUT_SRC_DIR)/mc_obct_top.v		\
		$(DUT_SRC_DIR)/mc_timing.v		\
		$(DUT_SRC_DIR)/mc_mem_if.v		\
		$(DUT_SRC_DIR)/mc_incn_r.v		\
		

##########################################################################
#
# Test Bench Sources
#
##########################################################################
_TOP_=test
TB_SRC_DIR=../../../bench/verilog
_TB_=		$(TB_SRC_DIR)/test_bench_top.v				\
		$(TB_SRC_DIR)/sync_cs_dev.v				\
		$(TB_SRC_DIR)/wb_mast_model.v				\
		$(TB_SRC_DIR)/160b3ver/adv_bb.v				\
		$(TB_SRC_DIR)/sram_models/MicronSRAM/mt58l1my18d.v	\
		$(TB_SRC_DIR)/sram_models/IDT71T67802/idt71t67802s133.v \
		$(TB_SRC_DIR)/sdram_models/2Mx32/mt48lc2m32b2.v		\
		

##########################################################################
#
# Misc Variables
#
##########################################################################

INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/"
LOGF=-LOGFILE .nclog
NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT

##########################################################################
#
# Make Targets
#
##########################################################################
simw:
	@@$(MAKE) -s sim ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES"

ss:
	signalscan -do waves/waves.do -waves waves/waves.trn &

simxl:
	verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR)	\
	$(_TARGETS_) $(_TB_)

sim:
	@@echo ""
	@@echo "----- Running NCVLOG ... ----------"
	@@$(MAKE) $(MS) vlog				\
		TARGETS="$(_TARGETS_)"			\
		TB="$(_TB_)"				\
		INCDIR=$(INCDIR)			\
		WAVES="$(WAVES)"
	@@echo ""
	@@echo "----- Running NCELAB ... ----------"
	@@$(MAKE) $(MS) elab				\
		ACCESS="$(ACCESS)" TOP=$(_TOP_)
	@@echo ""
	@@echo "----- Running NCSIM ... ----------"
	@@$(MAKE) $(MS) ncsim TOP=$(_TOP_)
	@@echo ""

hal:
	@@echo ""
	@@echo "----- Running HAL ... ----------"
	@@hal    +incdir+$(DUT_SRC_DIR)				\
		-NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK	\
		$(_TARGETS_)
	@@echo "----- DONE ... ----------"

clean:
	rm -rf	./waves/*.dsn ./waves/*.trn		\
		ncwork/.inc* ncwork/inc*		\
		./verilog.* .nclog hal.log

##########################################################################
#
# NCVLOG
#
##########################################################################

vhdl:
	ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG			\
		-WORK count -V93 hdl/counter.vhd
	ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG			\
		-WORK work -V93 $(TARGETS)

vlog:
	ncvlog $(NCCOMMON) $(LOGF) 				\
		-WORK work $(WAVES) $(TB) $(TARGETS) $(INCDIR)

##########################################################################
#
# NCELAB
#
##########################################################################

elab:
	ncelab	$(NCCOMMON) $(LOGF) -APPEND_LOG 		\
		-WORK work $(ACCESS) -NOTIMINGCHECKS		\
		work.$(TOP)

##########################################################################
#
# NCSIM
#
##########################################################################

ncsim:
	ncsim	$(NCCOMMON) $(LOGF) -APPEND_LOG			\
		-EXIT -ERRORMAX 10 work.$(TOP)


@


1.1
log
@

1) Changed Directory Structure
2) Fixed several minor bugs
@
text
@d2 1
d4 1
a4 1
#.QUIET
d6 19
a24 15
# test_bench/test_bench_top.v

MC_TARGETS=	../../../rtl/verilog/mc_top.v			\
		../../../rtl/verilog/mc_wb_if.v			\
		../../../rtl/verilog/mc_cs_rf.v			\
		../../../rtl/verilog/mc_rf.v			\
		../../../rtl/verilog/mc_adr_sel.v		\
		../../../rtl/verilog/mc_dp.v			\
		../../../rtl/verilog/mc_rd_fifo.v		\
		../../../rtl/verilog/mc_refresh.v		\
		../../../rtl/verilog/mc_obct.v			\
		../../../rtl/verilog/mc_obct_top.v		\
		../../../rtl/verilog/mc_timing.v		\
		../../../rtl/verilog/mc_mem_if.v		\
		../../../rtl/verilog/mc_incn_r.v
d27 14
a40 7
MC_TB=		../../../bench/verilog/test_bench_top.v		\
		../../../bench/verilog/sync_cs_dev.v		\
		../../../bench/verilog/wb_mast_model.v		\
		../../../bench/verilog/160b3ver/adv_bb.v		\
		../../../bench/verilog/sram_models/MicronSRAM/mt58l1my18d.v \
		../../../bench/verilog/sram_models/IDT71T67802/idt71t67802s133.v \
		../../../bench/verilog/sdram_models/2Mx32/mt48lc2m32b2.v	\
d43 5
a47 13
RT=		rt/tst_bench.vhd			\
		rt/8Kx8_vhdl.vhd			\
		../vga_lcd/hdl/vga.vhd			\
		../vga_lcd/hdl/dpm.vhd			\
		../vga_lcd/hdl/pgen.vhd			\
		../vga_lcd/hdl/wb_master.vhd		\
		../vga_lcd/hdl/colproc.vhd 		\
		../vga_lcd/hdl/fifo.vhd			\
		../vga_lcd/hdl/tgen.vhd			\
		../vga_lcd/hdl/wb_slave.vhd		\
		../vga_lcd/hdl/counter.vhd		\
		../vga_lcd/hdl/fifo_dc.vhd		\
		../vga_lcd/hdl/vtim.vhd			\
d49 3
d53 7
d61 2
a62 26
TOP=test
INCDIR="-INCDIR ../../../rtl/verilog/ -INCDIR ../../../bench/verilog/"
#ACCESS="-ACCESS +r"
#WAVES=-DEFINE WAVES

#rm -f ncwork/inca.linux.118.pak

mcwxl:
	verilog +incdir+verilog/ $(MC_TARGETS) $(MC_TB)

mcw:
	@@$(MAKE) -s mc ACCESS="-ACCESS +r" WAVES="-DEFINE WAVES"

mcss:
	signalscan -do waves/mc.do -waves waves/waves.trn &

mcss2:
	signalscan -do waves/mc2.do -waves waves/waves.trn &

mc_new:
	ncverilog +incdir+verilog +incdir+test_bench $(MC_TARGETS)

mc:
	@@$(MAKE) vlog TARGETS="$(MC_TARGETS) $(MC_TB)" INCDIR=$(INCDIR) WAVES="$(WAVES)" TOP=test
	@@$(MAKE) elab ACCESS="$(ACCESS)" TOP=test
	@@$(MAKE) sim  TOP=test
d64 3
a66 2
clean:
	rm -f ./waves/*.dsn ./waves/*.trn ./ncwork/inca* .ncwork/.inc*
d68 16
a83 2
er:
	grep ERROR .nclog
d86 6
a91 8
	@@hal	+incdir+./verilog/					\
		-NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK		\
		$(MC_TARGETS)

hala:
	@@hal	+incdir+./verilog/					\
		-NOS 							\
		$(MC_TARGETS)
d93 6
a98 1
#################################################################################
d102 1
a102 28
#################################################################################


rtt:
	ncvhdl -CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var	\
		-WORK count -NOCOPYRIGHT -V93			\
		-LOGFILE .nclog ../vga_lcd/hdl/counter.vhd

	ncvhdl -CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var	\
		-WORK ncwork -NOCOPYRIGHT  -V93			\
		-LOGFILE .nclog $(RT)

	ncvlog -CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var	\
		-WORK ncwork -NOCOPYRIGHT -UPDATE		\
		-LOGFILE .nclog $(WAVES) -INCDIR ./verilog/	\
		-INCDIR ./test_bench/  $(MC_TARGETS) 		\
		test_bench/sdram_models/2Mx32/mt48lc2m32b2.v

	ncelab -CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var	 \
		-WORK ncwork -NOCOPYRIGHT -ACCESS +r 		 \
		-LOGFILE .nclog -APPEND_LOG -NOTIMINGCHECKS	 \
		ncwork.testbench:test

	ncsim -CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var 	\
		-NOCOPYRIGHT -STATUS -LOGFILE .nclog 		\
		-APPEND_LOG -ERRORMAX 10 -NOKEY -UPDATE		\
		ncwork.testbench

d104 5
d111 2
a112 3
	ncvlog -CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var	\
		-WORK ncwork -NOCOPYRIGHT -UPDATE	\
		-LOGFILE .nclog $(WAVES) $(TARGETS) $(INCDIR)
d114 1
a114 3
# -IEEE1364

#################################################################################
d118 1
a118 1
#################################################################################
d121 3
a123 4
	@@ncelab -CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var	 \
		-WORK ncwork -NOCOPYRIGHT $(ACCESS) \
		-LOGFILE .nclog -APPEND_LOG -NOTIMINGCHECKS	 \
		ncwork.$(TOP)
d125 1
a125 2
# -IEEE1364
#################################################################################
d129 1
a129 1
#################################################################################
d131 3
a133 5
sim:
	@@ncsim -CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var 	\
		-NOCOPYRIGHT -STATUS -LOGFILE .nclog -EXIT	\
		-APPEND_LOG -ERRORMAX 10 -NOKEY -UPDATE	\
		ncwork.$(TOP)
@