head	1.1;
branch	1.1.1;
access;
symbols
	bg2_23:1.1.1.1
	bg2_22:1.1.1.1
	bg2_21:1.1.1.1
	bg2_20:1.1.1.1
	bg2_16:1.1.1.1
	bg2_15:1.1.1.1
	bg2_12:1.1.1.1
	bg2_07:1.1.1.1
	isorc2008_submission:1.1.1.1
	handbook_alpha_edition:1.1.1.1
	jtres2007_submission:1.1.1.1
	bg1_07:1.1.1.1
	bg1_06:1.1.1.1
	bg1_05:1.1.1.1
	TAL_101:1.1.1.1
	TAL_100:1.1.1.1
	jtres_submission:1.1.1.1
	wises06_submission:1.1.1.1
	lctes2006_submission:1.1.1.1
	rtgc_isorc2006:1.1.1.1.0.4
	isorc2006:1.1.1.1.0.2
	rtgc_paper:1.1.1.1
	bg1_00:1.1.1.1
	nohandle:1.1.1.1
	thesis:1.1.1.1
	arelease:1.1.1.1
	avendor:1.1.1;
locks; strict;
comment	@# @;


1.1
date	2004.02.19.13.24.10;	author martin;	state Exp;
branches
	1.1.1.1;
next	;

1.1.1.1
date	2004.02.19.13.24.10;	author martin;	state Exp;
branches;
next	;


desc
@@



1.1
log
@Initial revision
@
text
@FILES
{
	VHDL_FILE = ..\..\vhdl\config\cyc_conf.vhd;
}
COMPILER_SETTINGS_LIST
{
	COMPILER_SETTINGS = cyc_conf;
}
SIMULATOR_SETTINGS_LIST
{
	SIMULATOR_SETTINGS = cyc_conf;
}
SOFTWARE_SETTINGS_LIST
{
	SOFTWARE_SETTINGS = Debug;
	SOFTWARE_SETTINGS = Release;
}
@


1.1.1.1
log
@initial cvs import.
@
text
@@