head 1.2; access; symbols asyst_3:1.2 asyst_2:1.2 rel_25:1.2 rel_24:1.2 rel_23:1.2 rev_23:1.2 rel_22:1.2 highland_ver1:1.2 rel_21:1.2 rel_20:1.2 rel_19:1.2 rel_18:1.2 rel_17:1.2 rel_16:1.2 rel_15:1.2 rel_14:1.2 rel_13:1.2 rel_12:1.2 new_debug:1.2 old_debug:1.2 rev_11:1.2 rel_10:1.2 rel_9:1.2 rel_8:1.2 rel_7:1.2 rel_6:1.2 rel_5:1.2 rel_4:1.2 rel_3:1.2 sdram_test_working:1.2 rel_1:1.2 arelease:1.1.1.1 avendor:1.1.1; locks; strict; comment @# @; 1.2 date 2001.09.20.10.10.57; author mohor; state Exp; branches; next 1.1; 1.1 date 2001.09.13.13.49.19; author mohor; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2001.09.13.13.49.19; author mohor; state Exp; branches; next ; desc @@ 1.2 log @Working version. Few bugs fixed, comments added. @ text @////////////////////////////////////////////////////////////////////// //// //// //// README.txt //// //// //// //// //// //// This file is part of the SoC/OpenRISC Development Interface //// //// http://www.opencores.org/cores/DebugInterface/ //// //// //// //// //// //// Author(s): //// //// Igor Mohor //// //// igorm@@opencores.org //// //// //// //// //// //// All additional information is avaliable in this README.txt //// //// file. //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000,2001 Authors //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: README.txt,v $ // Revision 1.1.1.1 2001/09/13 13:49:19 mohor // Initial official release. // // Revision 1.2 2001/06/01 22:22:35 mohor // This is a backup. It is not a fully working version. Not for use, yet. // // Revision 1.1 2001/05/18 13:12:09 mohor // Header changed. All additional information is now avaliable in this README.txt file. // // PROJECT: SoC/OpenRISC Development (debug) Interface PROJECT AND DOCUMENTATION ON THE WEB: The project that this files are part of is avaliable on the opencores web page: http://www.opencores.org/cores/DebugInterface/ Documentation can also be found there. For direct download of the documentation go to: http://www.opencores.org/cgi-bin/cvsget.cgi/dbg_interface/doc/DbgSupp.pdf OVERVIEW (main Features): Development Interface is used for development purposes (Boundary Scan testing and debugging). It is an interface between the RISC, peripheral cores and any commercial debugger/emulator or BS testing device. The external debugger or BS tester connects to the core via JTAG port. The Development Port also contains a trace and support for tracing the program flow, execution coverage and profiling the code. dbg_tb.v is a testbench file. file_communication.v is used for simulating the whole design together with the debugger through two files that make a JTAG interface dbg_top.v is top level module of the development interface design COMPATIBILITY: - WISHBONE rev B.1 - IEEE 1149.1 (JTAG) KNOWN PROBLEMS (limits): - RISC changes Watchpoints and breakpoints on rising edge of the Mclk clock signal. Simulation should do the same. TO DO: - Add a WISHBONE master support if needed - Add support for boundary scan (This is already done, but not yet incorporated in the design) @ 1.1 log @Initial revision @ text @d48 3 d75 1 a75 1 http://www.opencores.org/cgi-bin/cvsget.cgi/DebugInterface/Doc/DbgSupp.pdf d89 6 a94 1 the code. d112 1 a112 2 - Add reset and cpu stall signals that are related to the RISCOP register - Add a WISHBONE master support d114 1 a114 1 - Signal RecSelDepend is not connected anywhere, yet. Read the pdf for details on that.@ 1.1.1.1 log @Initial official release. @ text @@