head 1.1; branch 1.1.1; access; symbols add:1.1.1.1 update:1.1.1.5 samiam95124:1.1.1; locks; strict; comment @# @; 1.1 date 2006.11.01.20.02.05; author samiam95124; state Exp; branches 1.1.1.1; next ; commitid 31604548faf04567; 1.1.1.1 date 2006.11.01.20.02.05; author samiam95124; state Exp; branches; next 1.1.1.2; commitid 31604548faf04567; 1.1.1.2 date 2006.11.11.12.04.53; author samiam95124; state Exp; branches; next 1.1.1.3; commitid 1fa44555b9f14567; 1.1.1.3 date 2006.11.16.10.29.37; author samiam95124; state Exp; branches; next 1.1.1.4; commitid 3f6c455c3ae54567; 1.1.1.4 date 2006.11.17.10.54.44; author samiam95124; state Exp; branches; next 1.1.1.5; commitid 3e01455d92754567; 1.1.1.5 date 2006.11.19.04.25.57; author samiam95124; state Exp; branches; next ; commitid 3554455fda5a4567; desc @@ 1.1 log @Initial revision @ text @Release 8.2.02i - Bitgen I.33 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx. "testbench" is an NCD, version 3.1, device xc3s1000, package ft256, speed -4 Opened constraints file testbench.pcf. Wed Nov 01 08:51:32 2006 C:\Xilinx\bin\nt\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:6 -g CclkPin:PullNone -g M0Pin:PullNone -g M1Pin:PullNone -g M2Pin:PullNone -g ProgPin:PullNone -g DonePin:PullNone -g TckPin:PullNone -g TdiPin:PullNone -g TdoPin:PullNone -g TmsPin:PullNone -g UnusedPin:PullNone -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Match_cycle:Auto -g Security:None -g DonePipe:No -g DriveDone:No testbench.ncd Summary of Bitgen Options: +----------------------+----------------------+ | Option Name | Current Setting | +----------------------+----------------------+ | Compress | (Not Specified)* | +----------------------+----------------------+ | Readback | (Not Specified)* | +----------------------+----------------------+ | CRC | Enable** | +----------------------+----------------------+ | DebugBitstream | No** | +----------------------+----------------------+ | ConfigRate | 6** | +----------------------+----------------------+ | StartupClk | Cclk** | +----------------------+----------------------+ | DCMShutdown | Disable** | +----------------------+----------------------+ | DCIUpdateMode | AsRequired** | +----------------------+----------------------+ | CclkPin | Pullnone | +----------------------+----------------------+ | DonePin | Pullnone | +----------------------+----------------------+ | HswapenPin | Pullup* | +----------------------+----------------------+ | M0Pin | Pullnone | +----------------------+----------------------+ | M1Pin | Pullnone | +----------------------+----------------------+ | M2Pin | Pullnone | +----------------------+----------------------+ | ProgPin | Pullnone | +----------------------+----------------------+ | TckPin | Pullnone | +----------------------+----------------------+ | TdiPin | Pullnone | +----------------------+----------------------+ | TdoPin | Pullnone | +----------------------+----------------------+ | TmsPin | Pullnone | +----------------------+----------------------+ | UnusedPin | Pullnone | +----------------------+----------------------+ | GWE_cycle | 6** | +----------------------+----------------------+ | GTS_cycle | 5** | +----------------------+----------------------+ | LCK_cycle | NoWait** | +----------------------+----------------------+ | Match_cycle | Auto** | +----------------------+----------------------+ | DONE_cycle | 4** | +----------------------+----------------------+ | Persist | No* | +----------------------+----------------------+ | DriveDone | No** | +----------------------+----------------------+ | DonePipe | No** | +----------------------+----------------------+ | Security | None** | +----------------------+----------------------+ | UserID | 0xFFFFFFFF** | +----------------------+----------------------+ | ActivateGclk | No* | +----------------------+----------------------+ | ActiveReconfig | No* | +----------------------+----------------------+ | PartialMask0 | (Not Specified)* | +----------------------+----------------------+ | PartialMask1 | (Not Specified)* | +----------------------+----------------------+ | PartialMask2 | (Not Specified)* | +----------------------+----------------------+ | PartialGclk | (Not Specified)* | +----------------------+----------------------+ | PartialLeft | (Not Specified)* | +----------------------+----------------------+ | PartialRight | (Not Specified)* | +----------------------+----------------------+ | IEEE1532 | No* | +----------------------+----------------------+ | Binary | No** | +----------------------+----------------------+ * Default setting. ** The specified setting matches the default setting. Running DRC. WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. DRC detected 0 errors and 4 warnings. Creating bit map... Saving bit stream in "testbench.bit". Bitstream generation is complete. @ 1.1.1.1 log @8080 CPU project @ text @@ 1.1.1.2 log @8080 CPU project @ text @d8 1 a8 1 Sat Nov 11 00:55:41 2006 d100 1 a100 1 WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is d106 1 a106 1 WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is d109 1 a109 1 WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is @ 1.1.1.3 log @8080 CPU project @ text @d8 1 a8 1 Wed Nov 15 08:55:02 2006 d100 1 a100 1 WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is d106 1 a106 1 WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is d109 1 a109 1 WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is d112 1 a112 10 WARNING:PhysDesignRules:812 - Dangling pin on block::. WARNING:PhysDesignRules:812 - Dangling pin on block::. WARNING:PhysDesignRules:812 - Dangling pin on block::. DRC detected 0 errors and 7 warnings. @ 1.1.1.4 log @8080 CPU project @ text @d8 1 a8 1 Thu Nov 16 20:16:39 2006 @ 1.1.1.5 log @8080 CPU project @ text @d8 1 a8 1 Sat Nov 18 17:16:32 2006 @