Project Name: CORDIC core

Description

CORDIC is an iterative algorithm to evaluate trigonometric, hyperbolic functions, and perform vector rotations.

Core Description


Structure

The CORDIC Processor core are built with three fundamental blocks: the pre-processor, the post-processor and the actual CORDIC core. The core is built using a pipeline of stage blocks. Each stage block represents a single step in the iteration processes.

The processor inputs accept two signed values, x and y coordinates of the endpoint of the given vector. The processor core rotates the origin vector to align it with the X-axis. After input data processing, the calculated value of the rotation angle and vector magnitude go out to the processor outputs.

Inputs/Outputs
Inputs
Input name Description
X The input coordinate of the vector in X-axis. The input is signed
Y The input coordinate of the vector in Y-axis. The input is signed
CLK Clock input
Outputs
Output name Description
Radius The vector magnitude
Angle The angle between the vector and X-axis

Features

In most of known algorithm implementations, vector rotating is carried out in the range of –90 to +90 degrees. However, the origin vector may be given in the range of –180 to +180 degrees. To use the algorithm over the entire range the inputs need to be manipulated to fit the range allowable for core processing. The pre-processor handles it. After getting the result angle, the post –processor corrects all modifications and places the CORDIC core’s results in the correct quadrant, taking into account the quadrant of the origin vector.

Still, there are some publications pointing that to use the algorithm the input vector must be put strictly in the range of –1(rad) to +1(rad). In the case when the vector is transformed from Cartesian to polar coordinates, the situation differs. In fact, the origin vector can be rotated to the X-axis through any angle even bigger than +/-90 degrees.

But using simple modifications, the input vector can be placed in the range of 0 to 45 degree in the pre-processor. It allows, in fact, getting three first significant bits of the result angle during this operation. Besides later the “first” iteration- with the 45 degrees rotation is unnecessary. The result vector after the last iterations increases not in 1,647 times, but in 1,647 / 1,41 =1,16 times. It also permits decrease conversion time by one cycle.

Current Status:

  • Design is coming up soon in VHDL from OpenCores CVS via cvsweb or via cvsget (cordic2)

 

Synthesis:

Synthesis results:
- Altera ACEX(EP1K50-1): ~1600 cells@90MHz
- Spartan-II (XC2S100-6): 669SLICES@98MHz 

Author & Maintainer(s):

About KharkovEnergoRemont

Mailto: khaer@opencores.org_NOSPAM

 

Mailing-list: