AVR32 AP7 - Cycle Counter Driver Documentation
This documents gives an example of the usage of the CPU Cycle counter. The cycle counter is a COUNT register, that increments once every clock. The count register can be used together with the COMPARE register to create a timer with interrupt functionality. The COMPARE register holds a value that the COUNT register is compared against. When the COMPARE and COUNT registers match, a compare interrupt request is generated. For all devices except the AT32AP700x COUNT is reset to 0 on COMPARE match.
This example shows how to use the COUNT register together with the COMPARE register to generate an interrupt periodically. Here is the operating mode of the example:
- At the beginning of the code, we check that initial default values of the COUNT and COMPARE registers are correct.
- Then, the COUNT & COMPARE interrupt mechanism is tested with a short delay. Messages are displayed on USART1. This delay is equal to (1/fCPU)*NB_CLOCK_CYCLE_DELAY_SHORT in case NB_CLOCK_CYCLE_DELAY_SHORT value is reloaded (83.3ms) or (1/fCPU)*NB_CLOCK_CYCLE_DELAY_LONG in case NB_CLOCK_CYCLE_DELAY_LONG value is reloaded (1.67s)
- Then the program infinitly loops, using the COUNT & COMPARE interrupt mechanism with a longer delay. Messages are displayed on USART1 and one of Led 1 through Led4 is on upon each COUNT & COMPARE match (Led1 -> Led2 -> Led3 -> Led4 -> Led1 ...and so on).
This software was written for the GNU GCC for AVR32 and IAR Systems compiler for AVR32. Other compilers may or may not work.
All AVR32 devices. This example has been tested with the following setup:
-
STK1000 development board
CPU speed:
20 Mhz.
This example has been tested with the following configuration:
- USART1 connected to a PC serial port via a standard RS232 DB9 cable;
- PC terminal settings:
- 115200 bps,
- 8 data bits,
- no parity bit,
- 1 stop bit,
- no flow control.
For further information, visit
Atmel AVR32.
Support and FAQ:
http://support.atmel.no/