Re: [fpu] fdiv

[Rudolf Usselmann <rudi@inet.co.th>]

> hi all,
> 
> I attached to teh email teh fdiv core it is not yet
> ready there are some bugs and things to be covered but
> I want your comments on teh code since it is my first
> verilog code.

You must also do rounding and post normalisation.

In Verilog, all sequential assignments should be non blocking,
and I would recommend a 1 time unit delay for them as well. This
is because some simulators might enter race conditions if you
don't do this. So all sequential assignment should look something
like:

always @(posedge clk)
    Q <= #1 D;


> Could you please let me know what the interfaces of
> the other cores so as to make it compatible with them.

There is no need for a reset.

input           clk;
input [31:0]    opa, opb;
output [31:0]   out;
output          div_zero, overflow, underflow, inexact, snan;
output          "whatever other exception you can detect";

> 
> Regards
> Jamil Khatib

rudi