[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [usb] help on USB 2.0!



On Sat, 2003-05-17 at 17:29, Sostene Mannino wrote:
> Dear Rudolf,
> I am a student of electronic engineering in the University of Palermo
> (Italy) and I'm working on USB interface!
> I'm testing your Core USB 2.0 and I pheraps have found some errors.
> For example in usbf_defines: the row "define USBF_T1_C_5_MS         
> 7' d50"         I have changed it, in "define USBF_T1_C_5_MS         
> 7' d80".

Yes, that was a typo, The comments in the source code are
correct however ...


> Further example: in usbf_utmi_ls   I have changed   "reg      [5:0]   
> idle_cnt_2"   in   "reg       [6:0]    idle_cnt_2"   because
> idle_cnt_2   wasn't able to count up to 5ms................and so on!

Hugh ? Why would idle_cnt2 count to 5mS ?
'idle_cnt2' only needs to be 6 bits wide.
There is nothing wrong with that.

> I'm testing your core, but could you suggest me any tool for verifying
> the IP Core? 

Yes, a good verilog simulator should do it.

> Could you give me any suggestions about it?
> Besides I'm making a function for interfacing the Core, which
> manages the data change with a flash memory.
> Could you give me suggestions where to find any data?
> I thank you
>  
> Sostene Mannino

Regards,
rudi               
-------------------------------------------------------
www.asics.ws  -- Solutions for your ASIC/FPGA needs ---
---------------- FPGAs * Full Custom ICs * IP Cores ---
* * * FREE IP Cores  --> http://www.asics.ws/ <-- * * *



--
To unsubscribe from usb mailing list please visit http://www.opencores.org/mailinglists.shtml