Re: [usb] Please help with a USB DPLL

[Rudolf Usselmann <rudi@asics.ws>]

On Sat, 2003-05-17 at 00:27, mdennis97@hotmail.com wrote: 
> > > 
> > > Why not use a static 12Mhz clock for the transmit module?For 
> > many 
> > > applications, 12Mhz clock is always available. 
> > 
> > Sure, if all you need is Low Speed, that that would work. 
> 
> One thing should be verified : if only Low Speed is required, the fs_ce 
> signal width must be keep 1 clk width(48 Mhz). And in this condition, 
> fs_ce works 1.5 Mhz. If the above two requirements are met, your 

Yes I totally agree with you. That is correct !

> usb_tx_phy module might work except PRE pid which should be send in 
> Full Speed.

I believe the PRE PID should be stripped by an separate block.
This would make the entire design easier. Just watch any traffic
for PRE PIDs (at the beginning of a new packet), if you see it
strip it if not, just pass it through.

Good Luck !

-- 
rudi               
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