Re: [usb] Please help with a USB DPLL

[Rudolf Usselmann <rudi@asics.ws>]

On Thu, 2003-05-15 at 15:43, mdennis97@hotmail.com wrote:
> Thanks, Mr. rudi:
>   The usb phy you have contributed uses 48mhz as its clock.Taking into 
> account the host side applications, host controller may signal in low 
> speed and full speed. In this condition, I don't know if a single phy can 
> deal with those tasks. If it does, when working at low speed, can we 
> connect the clk signal of the phy to a 6mhz clock which may be derived 
> from the 48mhz?
>   Furthermore, after having completed the low speed transaction, the 
> phy clock should be switched back to 48mhz. Does this suppositon work?
> 
> Regards
> 
> Dennis

Well, this phy was designed with full speed in mind only.

Switching clocks is always a bad idea. Take a closer look
how the DPLL works and how the actual 12Mhz clock is generated.
If I remember correctly, everything runs at 48Mhz all the
time, and I use clock enable to advance the rx and tx logic
at a 1/4 speed 9e.g. 12 Mhz). My guess would be that it
would be a much cleaner solution to modify the DPLL to
support LS speed mode.

If you do make these modifications, please submit your
work to OpenCores as well.

rudi
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