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Re: [usb] USB CORE IN VHDL





----- Original Message ----- 
From: gr6@u...  
To: usb@o...  
Date: Tue, 01 May 2001 22:40:45 +0100 (BST) 
Subject: [usb] USB CORE IN VHDL 

> 
> 
> HELLO, 
> I AM LOOKING FOR FREE USB (V:2.0) CORE WRITTEN IN VHDL. 
> 
> THANK YOU 
>

Hi dear unknown
i am searching for free usb cores like you.
but i didn't find a Synthetizeable usb core for my studental 
project "transferring ecg signal from usb bus".
do you have ver 1.0  usb Synthetizeable  core  ??
if you have please help me for my project. 
bahador makki biomedical eng. ms.student
thanks ,
--
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