[usb] some question about the code of the USB function core

[Jiang daosan <jiangdaosan@21cn.com>]

Hi,Rudi and all:

   I have some questions about the USB function core.
The first is that how can I re-simulate the core as I cannot
find anything in the dictory of bench. I want to learn how
to get a full simulation about the core.

The second is that I have seen some code in the module of the core
like that following :

always @(posedge clk)
	clr_sof_time <= #1 frame_no_we;
                    ~~~~~ that means to assign the value after one unit time 

In my opinion, to add one unit time delay in the code is to minimize
the difference between the RTL simulation and the synthesized gate-level
simulation. But that code may not be supported by the synthesis tools.
Is that true ? How can I change the core into synthesisable ?

Thanks for your answer.

Best regards.


Jiang daosan
jiangdaosan@21cn.com


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