RE: [usb] RXValid signal

["santhi lakshminarayanan" <santhi.lakshminarayanan@wipro.com>]

Title:

Hello,

Please find the answers below:
1.  a) A bit stuff error occurs during reception, when a consecutive 6 "1"s in the data stream is not succeeded by a '0'. This indicates that a bit stuffing has not occured at the transmitting end or some corruption has occured in the reception. Either case, it is an error detected due to bit stuffing in the reception.

      b) 8 stuffed bits are accumulated over a continuous data stream, but may not be consecutive. There can be 6 '1's and a '0', followed by a different pattern which does not require bit stuffing, and then another 6'1's and a '0' which makes the count of unstuffed bits to increment and so on.

 

2. In FS mode, ideal number of CLK cycles per byte time is 40 (which can be 45 or 50 for 1 or 2 bit stuffs respectively). RXValid is asserted only one CLK cycle per byte time where we need to ensure that data is also valid on the data bus. Till next data byte is available RXValid will not be asserted, Following the state machine, RXValid is asserted whenever RX Data state is entered. 

 

3.  !Data indicates that data is not available to be sent on the data bus. This could be because of bit unstuffs or as in the case of FS mode, where data is available only once in 40-50 CLK cycles (and for the rest of the CLK cycles, data is not available).

 

I hope these answers your questions.

 

Regards,

Santhi.

****************************************************
Santhi. L
Senior Engineer- VLSI/System Design
Wipro Technologies,
72, Electronic City,
Bangalore - 561229, India.
Tel - +91-80-8520408 Extn- 4263
Fax - +91-80-8520478
E-mail - santhi.lakshminarayanan@wipro.com 
Web -    www.wipro.com

****************************************************


>>-----Original Message-----
>>From: owner-usb@opencores.org [mailto:owner-usb@opencores.org]On Behalf
>>Of Luis J. Perez
>>Sent: Wednesday, September 05, 2001 10:25 PM
>>To: usb@opencores.org
>>Subject: [usb] RXValid signal
>>
>>
>>Hello everybody,
>>
>>If anyone can help me, I have some questions about RXValid signal of USB
>>2.0 Transceiver.
>>
>>1) In USB Trans spec (page 21) explains that "Each time 8 stuffed bits
>>are accumulated the state machine will enter the RX Data Wait state,
>>negating RXValid thus skipping a byte time". My questions:
>>- A bit stuff error supposes that after 6 ones in NRZ there is another
>>one (not a cero as supossed if well stuffed) ???
>>- "8 stuffed bits" means consecutive bits?
>>- This 8 stuffed bits would be a NRZ = 111111 0 111111 0 111111 0 111111
>>0 ... until 8 zeros ... ?
>>
>>2) The assertion of RXValid differs in HS and FS modes. For HS is
>>explained in Figure 5 of referred specs (CLK could be 30 or 60 MHz).
>>- For FS would be like this?: CLK=48MHz --> RXValid is only asserted
>>during 1st cycle of the 32 for each byte, isn't it?
>>- So, for FS mode, RXValid must be negated just after cahnging to RX
>>Data state in the FSM of Figure 6 (Transceiver specs).
>>
>>3) About Figure 6:
>>- It must work @ 48 MHz (FS) or 30-60 MHz (HS), just the CLOCKOUT, isn't
>>it?
>>- What does the "!Data" mean? Does it mean the hold register is not
>>full? There is a stuffed bit?
>>
>>Well, I think that's enough for the first time I write to the list.
>>
>>As you have seen, I'm designing a transceiver in FS mode to use it with
>>the USB 2.0 core of OPENCORES. This will help me (making some little
>>changes to do a HS mode model) to test this core (I wish). If anyone
>>needs help...
>>
>>Thanks,
>>
>>
>>========================================================
>>Luis Jose Perez Lafuente              luis.perez@ds2.es
>>Design Engineer
>>Digital Design Department
>>
>>Design of Systems on Silicon          http://www.ds2.es
>>Av. Charles Robert Darwin, 2          Phone.  +34-96-136 60 04
>>Parc Tecnologic                                         Ext. 152
>>46980 Paterna (VALENCIA)              FAX     +34-96-136 62 50
>>SPAIN
>>========================================================
>>--
>>To unsubscribe from usb mailing list please visit
>>http://www.opencores.org/mailinglists.shtml
>>

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