Re: [pci] TOP.v to TOP.sch

[Marco Buffa <marcobuffa@lombardiacom.it>]

Nico Weling ha scritto:
> This will successfully synthesize but the card is not be seen by the system (lspci)!
> What did I wrong???
FPGA Express works with mixed (VHDL and verilog) projects :-)

You can create your own part in VHDL and connect it to the core with a 
hierarchical block written in VHDL...
I confirm it works very well.

I don't like schematics: I can't see what I'm really doing :-(

Regards.
-- 
Marco (Politecnico di Milano, Italy)

"Qui se accendessero le luci e riabbassassero le luci
ci troverebbero tutti in piedi con gli occhi aperti, qui"
(Ivano Fossati, "Sigonella")

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