RE: [pci] Implementing the PCI-CRT project using ISE 5.2 & the supplied project

["Tadej Markovic" <tadejm@flextronics.si>]

Hi!

In PCI bridge you have FIFO buffer for posted writes and delayed reads. This
FIFO can have normal Flip-Flop RAM or distributed RAM or Xilinx Block RAM or
Altera RAM (we didn't prepare for this because we don't have Altera board
and their software) or Whatever RAM from any vendor.
So this two files are RAMs for Artisan and VirtualSilicon libraries when you
want to put your core in ASIC. They are not free and we are not allowed to
publish them, but I think that you will not need them for now :)

I hope this helps.

Best regards,
	Tadej



> -----Original Message-----
> From: owner-pci@opencores.org
> [mailto:owner-pci@opencores.org]On Behalf
> Of matts@commtech-fastcom.com
> Sent: 13. junij 2003 23:18
> To: pci@opencores.org
> Subject: [pci] Implementing the PCI-CRT project using ISE 5.2 & the
> supplied project
>
>
> I am trying to implement the PCI-CRT test project and I am
> using Xilinx's
> ISE 5.2.  I have the ise-openpci.npl project file and I have
> added all the
> correct sources to the project to get it as close to
> synthesizable as I
> can get it.
>
> Now I am seeing two source files that I can't seem to find anywhere:
> art_hsdp_256x40 and vs_hdtp_64x40.
>
> Can someone tell me what these are and how I can get them into the
> project?
>
> Thanks
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