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Re: Re: [pci] PCI core in VHDL and PCI bursts

Title:
Hello again!

In my implementation the wishbone pci master and slave are point to point connected on two separate wishbone buses towards an AMBA bridge I have developed. This means the CYC is not used but hardwired to '1'. The same holds for SEL.

During the RTY responses the pci target has prefetched four words and should be set for a nice smooth burst over the pci bus.
What happens is that the PCI inititator just as during the earlier stb:s that were responded with retry only tries to read one word from the PCI target (ie. the FRAME# only go low for one cycle). This result in the target transfering the first word in the FIFO and flushes the rest. When the next read cycle appear on the PCI bus prefetching starts all over again thus generating very low band-width. No data is corrupted.

I append som ascii art to support my text.

Signals are in respect to pci bridge
			  		                                 __
ACK_O		 _______________________________________________________|  |___________
		       __        __        __        __        __                  __
TRY_O		 _____|	 |______|  |______|  |______|  |______|  |________________|  |
              	   ______    ______    ______    ______    ______    ______    ______
STB_I            _|	 |__|      |__|      |__|      |__|      |__|      |__|      |_
                   ______________________________________________________________
CAB_I            _|                                                              |_____
                 ______________________________________________________________________
CYC_I             			                          
                 ______________________________________________________________________
SEL_I                                                                                      


Regards, Daniel
          Hello!

First regarding the VHDL version - it is not available yet and I don't know
whether any work is being done regarding that.
You should probably contact the person which posted the original message.

Regarding Read bursts:
CAB_I signal should be used concurrently with CYC_I signal, not STB_I
signal.
If you intend to burst read, you should put CYC_I and CAB_I to 1
simultaneously, while STB_I is used for
bus throttling.
I'll have to take a look into code regarding your other question when I have
some time.

Regards,
Miha Dolenc