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Gentlemen:
Please bear with me if I stumble here,
this is my first Verilog experience. I have setup a system with Xilinx ISE
Foundation (the new one) and I have Modelsim 5.6a running as a simulator. I can
compile the pci_bridge with no errors and even see PAR (Place and Route) show
what looks like a valid floorplan. Based on that, I think that I have the bridge
options in pci_user_constants at least set to no error in compilation (guest, 2
pci images, 2 wb images, no define of either FPGA or XILINX [issue with
RAMB4_S16_S16 but thats another story, I think]).
I can also both compile and simulate
with Modelsim. In running the simulator on the system.v file, I can see the
first error I get is basically "*** monitor - PCI Test 1 OE signals have X's".
So, can anyone help point me on the
correct path to understanding and appreciating this wonderful (and complicated)
piece of code that I have been studying for a couple of weeks now and just
gotten to where I can now run simulation. I am kinda new at this and a bit lost
right now.
Maybe I have a host setting somewhere
in the bench which should be guest, or maybe I have some option in
pci_blue_options.vh set for external arbiter when it should be internal. Quite
frankly, I don't know where to go next.
A verbose answer for a newbie would be
very appreciated.
Charles
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