RE: [pci] a puzzle of pci output signals

["Tadej" <tadej@opencores.org>]

Hi!

Yes, outputs MUST be registered. And yes again, because of that you can not
directly use
the state machine of PCI Local Bus Spec. But in the specs there is written,
that their state
machine is only for a reference; if there are any differencies between state
nachine and the
text in specs, then the text is correct.
Because registered outputs are not directly the PCI spec isue, they didn't
put that into their
state machine. But you need that in ASIC and in FPGA; in ASIC every output
must be
registered, in FPGA you won't meet timings if outputs are not registered.

I must worn you, that if you will put your design into the FPGA, you will
have a lot of problems
with meeting timign constraints for input signals. When you will come there,
post an email.
BTW: Our PCI bridge design is finished, and we are abaout to finish the
Testbench.

Best regards,
		Tadej


-----Original Message-----
From: owner-pci@opencores.org [mailto:owner-pci@opencores.org]On Behalf Of
sumnow
Sent: Thursday, November 22, 2001 2:30 AM
To: pci@opencores.org
Subject: [pci] a puzzle of pci output signals


hi all, i am doing a host-pci bridge design. now i'm puzzled with the
following:

should i register the pci output signals from state machine? if i do so,
perhaps i can not use the state machine of PCI Local Bus Spec. but i do
think i should register the outputs considering the synthesis.

any suggestions are welcome, thanks a lot.

            sumnow
            sumnow@263.net


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