Hi Guys
sorry for this delay and thanks for your offers!
I think I'll stay with the verification, starting on PCI side.
Miha, have you (or Tadej) specified the language of this project
{Verilog, VHDL}? And what is the tool chain you re using?
Ovidiu, are you porting the PCISim to Verilog?
Cheers,
Oliver