[pci] Request for help on a PCI target

[SV SUBRAMANIAN <svs@vsnl.com>]

My name is Visvanath Subramanian. I am doing my final year BE(
Electronics and Communication Engineering) at PSG College of Technology,

Coimbatore, India.I am  building  a PCI target device
that reads the BIOS POST status codes that is written continuously to
I/O Port 80H during the Power on Self Test (POST) process at system
bootup

        I am having some problems regarding the address decoder. I have
no idea as to how the IO Adress (80H in this case) is translated to the
PCI 32 bit Address space. Will anybody be able to help in this regard,
or
point me in some direction regarding this?

        I am now working on the PCI Finite state machine (a target
sequencer machine). I do not have the PCI SIG Specifications. I am using

"PCI System Architecture" , by Tom Shanley and Don Anderson, Mindshare
Inc, Addison Wesley. Also I would like to know if Read and Write are to
be
defined as seperate states according to  the PCI Specs. (Right now, the
states i am defining  are - IDLE,BACKOFF,B_BUSY, S_DATA, TURN_AR).

I would be thankful if anybody can provide me with any help  in this
regard...

Thanks in advance,
Visvanath Subramanian

  Please reply to: svs@vsnl.com