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Hello again!
In OR1000 architecture you define a set of
configuration registers (i.e. DCCR, ICCR, IMMUCR...). In particular, i am
interested in Data Cache Configuration Register.
There is a group of bits NCW (Number of Cache Ways)
that allows you to choose among several number of ways, from 1 way to 32 ways.
My question is: if I want a full-associative cache in my implementation, how
should I set this group of bits. Theoretically, i could not implement a
full-associative cache greater than 32 blocks (32 ways with one block per way)
but I don't think this would be an appropiate
restriction.
Can you help?
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