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Re: [openrisc] Problem about configure the gcc with "--target=or32-uclinux"
Hi,
Checkout these modules from opencores CVS:
# cvs -d :pserver:cvs@cvs.opencores.org:/home/oc/cvs -z9 co -r tn_m001 or1k/binutils
# cvs -d :pserver:cvs@cvs.opencores.org:/home/oc/cvs -z9 co -r tn_m001 or1k/gcc
# cvs -d :pserver:cvs@cvs.opencores.org:/home/oc/cvs -z9 co or1k/newlib-1.10.0
# cvs -d :pserver:cvs@cvs.opencores.org:/home/oc/cvs -z9 co or1k/rtems-20020807
prepare build directory, let's say in or1k directory:
# cd or1k
# mkdir bb
Build binutils:
# mkdir bb/binutils
# cd bb/binutils
# ../../binutils/configure --target=or32-rtems --prefix=/opt/or32-rtems
# make all install
export path:
# export PATH="/opt/or32-rtems/bin:$PATH"
Build gcc:
# mkdir bb/gcc
# cd or1k/gcc
# ln -fs ../newlib-1.10.0/newlib/ .
# ./contrib/egcs-update --touch
# cd ../bb/gcc
# ../../gcc/configure --target=or32-rtems --with-gnu-as --with-gnu-ld --with-newlib
--verbose --enable-threads --prefix=/opt/or32-rtems --enable-languages="c"
# make all install
Build rtems:
# mkdir bb/rtems
# cd bb/rtems
# ../../rtems-20020807/configure --target=or32-rtems
# make all
This should successfully build rtems toolchain and binaries.
Sample programs are then located in bb/rtems/or32-rtems/orp/samples
I attached configuration file for or1ksim that is configured properly to
run build samples. Also note, that you have to create uart0.rx and uart0.tx
files in a directory you are running or1ksim from (please look inside sim.cfg
for details). These are console input/output.
# touch uart0.rx uart0.tx
You have to use or1k/binutils and or1k/gcc with tag tn_m001, and or1k/newlib-1.10.0.
We are switching rtems binary format from coff to elf32-or32 and transition
is not complete yet.
regards,
Ivan
xu hu wrote:
20020913143819.75455.qmail@web14601.mail.yahoo.com">
Hi, come on, give me some advice.
when i set the target to or32-rtems, i have the
toolchain compiled successful, but when i configure
the
rtems, there is another error, or32-rtems-gcc can't
compile correctly, so i write a simple c code, then
compile it with or32-rtems-gcc, ld says " target
elf32-or32 not found"
why? Help me please.
giro.
--- xu hu <giro_cn@yahoo.com> wrote:
Today, i get the source of gcc from the cvs, but
when
i try to compile it, i meet some problem,
"#> ../gcc/configure --target=or32-uclinux ....."
run error.
it says " Invalid configuration 'or32- \
uclinux':system:'uclinux' not recognized.
Unrecognized target system name or32-uclinux"
why?
Any help will be appreciated!
Thanks.
giro.
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/* sim.cfg -- Simulator configuration script file
Copyright (C) 2001, Marko Mlinar, markom@opencores.org
This file includes a lot of help about configurations and default one
This file is part of OpenRISC 1000 Architectural Simulator.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
/* INTRODUCTION
The or1ksim have various parameters, which can be set in configuration
files. Multiple configurations may be used and switched between at
or1ksim startup.
By default, or1ksim loads condfiguration file from './sim.cfg' and if not
found it checks '~/.or1k/sim.cfg'. If even this file is not found or
all parameters are not defined, default configuration is used.
Users should not rely on default configuration, but rather redefine all
critical settings, since default configuration may differ in newer
versions of the or1ksim.
If multiple configurations are used, user can switch between them by
supplying -f <filename.cfg> option when starting simulator.
This file may contain (standard C) only comments - no // support.
Configure files can also be included, using:
include "file_name_to_include"
Like normal configuration file, this file is divided in sections,
where each section is described in detail also.
Some section also have subsections. One example of such subsection is
block:
device <index>
instance specific parameters...
enddevice
which creates a device instance.
*/
/* MEMORY SECTION
This section specifies how is initial memory generated and which blocks
it consist of.
type = random/unknown/pattern
specifies the initial memory values. 'random' parameter generate
random memory using seed 'random_seed' parameter. 'pattern' parameter
fills memory with 'pattern' parameter and 'unknown' does not specify
how memory should be generated - the fastest option.
random_seed = <value>
random seed for randomizer, used if type = random
pattern = <value>
pattern to fill memory, used if type = pattern
nmemories = <value>
number of memory instances connected
instance specific:
baseaddr = <hex_value>
memory start address
size = <hex_value>
memory size
name = "<string>"
memory block name
ce = <value>
chip enable index of the memory instance
delayr = <value>
cycles, required for read access, -1 if instance does not support reading
delayw = <value>
cycles, required for write access, -1 if instance does not support writing
16550 = 0/1
0, if this device is uart 16450 and 1, if it is 16550
log = "<filename>"
filename, where to log memory accesses to, no log, if log command is not specified
*/
section memory
/*random_seed = 12345
type = random*/
pattern = 0x00
type = unknown /* Fastest */
nmemories = 2
device 0
name = "FLASH"
ce = 0
baseaddr = 0x00000000
size = 0x00200000
delayr = 10
delayw = -1
enddevice
device 1
name = "RAM"
ce = 1
baseaddr = 0x10000000
size = 0x02000000
delayr = 2
delayw = 4
enddevice
end
/* IMMU SECTION
This section configures Instruction Memory Menangement Unit
enabled = 0/1
whether IMMU is enabled
(NOTE: UPR bit is set)
nsets = <value>
number of ITLB sets; must be power of two
nways = <value>
number of ITLB ways
pagesize = <value>
instruction page size; must be power of two
entrysize = <value>
instruction entry size in bytes
ustates = <value>
number of ITLB usage states (2, 3, 4 etc., max is 4)
hitdelay = <value>
number of cycles immu hit costs
missdelay = <value>
number of cycles immu miss costs
*/
section immu
enabled = 0
nsets = 32
nways = 1
pagesize = 8192
hitdelay = 0
missdelay = 0
end
/* DMMU SECTION
This section configures Data Memory Menangement Unit
enabled = 0/1
whether DMMU is enabled
(NOTE: UPR bit is set)
nsets = <value>
number of DTLB sets; must be power of two
nways = <value>
number of DTLB ways
pagesize = <value>
data page size; must be power of two
entrysize = <value>
data entry size in bytes
ustates = <value>
number of DTLB usage states (2, 3, 4 etc., max is 4)
hitdelay = <value>
number of cycles immu hit costs
missdelay = <value>
number of cycles immu miss costs
*/
section dmmu
enabled = 0
nsets = 32
nways = 1
pagesize = 8192
hitdelay = 0
missdelay = 0
end
/* IC SECTION
This section configures Instruction Cache
enabled = 0/1
whether IC is enabled
(NOTE: UPR bit is set)
nsets = <value>
number of IC sets; must be power of two
nways = <value>
number of IC ways
blocksize = <value>
IC block size in bytes; must be power of two
ustates = <value>
number of IC usage states (2, 3, 4 etc., max is 4)
hitdelay = <value>
number of cycles ic hit costs
missdelay = <value>
number of cycles ic miss costs
*/
section ic
enabled = 0
nsets = 512
nways = 1
blocksize = 16
hitdelay = 0
missdelay = 0
end
/* DC SECTION
This section configures Data Cache
enabled = 0/1
whether DC is enabled
(NOTE: UPR bit is set)
nsets = <value>
number of DC sets; must be power of two
nways = <value>
number of DC ways
blocksize = <value>
DC block size in bytes; must be power of two
ustates = <value>
number of DC usage states (2, 3, 4 etc., max is 4)
load_hitdelay = <value>
number of cycles dc load hit costs
load_missdelay = <value>
number of cycles dc load miss costs
store_hitdelay = <value>
number of cycles dc load hit costs
store_missdelay = <value>
number of cycles dc load miss costs
*/
section dc
enabled = 0
nsets = 512
nways = 1
blocksize = 16
load_hitdelay = 0
load_missdelay = 0
store_hitdelay = 0
store_missdelay = 0
end
/* SIM SECTION
This section specifies how should sim behave.
verbose = 0/1
whether to print out extra messages
debug = 0-9
= 0 disabled debug messages
1-9 level of sim debug information, greater the number more verbose is
the output
profile = 0/1
whether to generate profiling file 'sim.profile'
prof_fn = "<filename>"
filename, where to generate profiling info, used
only if 'profile' is set
mprofile = 0/1
whether to generate memory profiling file 'sim.mprofile'
mprof_fn = "<filename>"
filename, where to generate memory profiling info, used
only if 'mprofile' is set
history = 0/1
whether instruction execution flow is tracked for
display by simulator hist command. Useful for
back-trace debugging.
iprompt = 0/1
whether we strart in interactive prompt
exe_log = 0/1
whether execution log should be generated
exe_log = default/hardware/simple/software
type of executed log, default is used if not specified
exe_log_start = <value>
index of first instruction to start log with, default = 0
exe_log_end = <value>
index of last instruction to end log with; not limited, if omitted
exe_log_marker = <value>
<value> specifies number of instructions before horizontal marker is
printed; if zero, markers are disabled (default)
exe_log_fn = "<filename>"
where to put execution log in, used only if 'exe_log'
is set
spr_log = 0/1
whether log of writes/reads to/from sprs should be generated
spr_log_fn = "<filename>"
where to put sprs writes/reads in log, used only if 'spr_log'
is set
clkcycle = <value>[ps|ns|us|ms]
specifies time measurement for one cycle
*/
section sim
/* verbose = 1 */
debug = 4
profile = 0
prof_fn = "sim.profile"
mprofile = 0
mprof_fn = "sim.mprofile"
history = 1
/* iprompt = 0 */
exe_log = 0
exe_log_type = hardware
exe_log_start = 0
exe_log_end = 0
exe_log_marker = 0
exe_log_fn = "executed.log"
spr_log = 0
spr_log_fn = "spr.log"
clkcycle = 100ns
end
/* SECTION VAPI
This section configures Verification API, used for Advanced
Core Verification.
enabled = 0/1
whether to start VAPI server
server_port = <value>
TCP/IP port to start VAPI server on
log_enabled = 0/1
whether logging of VAPI requests is enabled
hide_device_id = 0/1
whether to disable logging of device id (for compatability with old version)
vapi_fn = <filename>
specifies filename where to log into, if log_enabled is selected
*/
section VAPI
enabled = 0
server_port = 9998
log_enabled = 0
vapi_log_fn = "vapi.log"
end
/* CPU SECTION
This section specifies various CPU parameters.
ver = <value>
rev = <value>
specifies version and revision of the CPU used
upr = <value>
changes the upr register
sr = <value>
sets the initial Supervision Register value
superscalar = 0/1
whether CPU is scalar or superscalar
(modify cpu/or32/execute.c to tune superscalar model)
hazards = 0/1
whether data hazards are tracked in superscalar CPU
and displayed by the simulator r command
dependstats = 0/1
whether inter-instruction dependencies are calculated
and displayed by simulator stats command.
raw_range = <value>
range in cycles for raw register over time analysis, 0 = disabled
sbuf_len = <value>
length of store buffer (<= 256), 0 = disabled
*/
section cpu
ver = 0x1200
rev = 0x0001
/* upr = */
sr = 0x00008003
superscalar = 0
hazards = 0
dependstats = 0
raw_range = 0
sbuf_len = 0
end
/* PM SECTION
This section specifies Power Menagement paramaters
enabled = 0/1
whether power menagement is enabled
*/
section pm
enabled = 0
end
/* BPB SECTION
This section specifies how branch prediction should behave.
enabled = 0/1
whether bpb is enabled
btic = 0/1
enable branch target instruction cache model
sbp_bf_fwd = 0/1
whether static branch prediction for l.bf uses forward prediction
sbp_bnf_fwd = 0/1
whether static branch prediction for l.bnf uses forward prediction
hitdelay = <value>
number of cycles bpb hit costs
missdelay = <value>
number of cycles bpb miss costs
*/
section bpb
enabled = 0
btic = 0
sbp_bf_fwd = 0
sbp_bnf_fwd = 0
hitdelay = 0
missdelay = 0
end
/* DEBUG SECTION
This sections specifies how debug unit should behave.
enabled = 0/1
whether debug unit is enabled
gdb_enabled = 0/1
whether to start gdb server at 'server_port' port
server_port = <value>
TCP/IP port to start gdb server on, used only if gdb_enabled
is set
vapi_id = <hex_value>
Used to create "fake" vapi log file containing the JTAG proxy messages.
*/
section debug
enabled = 1
gdb_enabled = 0
server_port = 9999
vapi_id = 0xFFFF
end
/* MC SECTION
This section configures the memory controller
enabled = 0/1
whether memory controller is enabled
baseaddr = <hex_value>
address of first MC register
POC = <hex_value>
Power On Configuration register
*/
section mc
enabled = 0
baseaddr = 0x60000000
POC = 0x00000008 /* Power on configuration register */
end
/* UART SECTION
This section configures UARTs
nuarts = <value>
make specified number of instances, configure each
instance within device - enddevice construct.
instance specific:
baseaddr = <hex_value>
address of first UART register for this device
rxfile = "<filename>"
filename, where to read data from
txfile = "<filename>"
filename, where to write data to
irq = <value>
irq number for this device
16550 = 0/1
0, if this device is uart 16450 and 1, if it is 16550
jitter = <value>
in msecs... time to block, -1 to disable it
vapi_id = <hex_value>
VAPI id of this instance
*/
section uart
nuarts = 1
device 0
baseaddr = 0x80000000
irq = 2
rxfile = "uart0.rx"
txfile = "uart0.tx"
jitter = -1 /* async behaviour */
enddevice
end
/* DMA SECTION
This section configures DMAs
ndmas = <value>
make specified number of instances, configure each
instance within device - enddevice construct.
instance specific:
baseaddr = <hex_value>
address of first DMA register for this device
irq = <value>
irq number for this device
vapi_id = <hex_value>
VAPI id of this instance
*/
section dma
ndmas = 0
/*
device 0
baseaddr = 0x90000000
irq = 4
enddevice
*/
end
/* ETHERNET SECTION
This section configures ethernets
nethernets = <value>
make specified number of instances, configure each
instance within device - enddevice construct.
instance specific:
baseaddr = <hex_value>
address of first ethernet register for this device
dma = <value>
which controller is this ethernet "connected" to
irq = <value>
ethernet mac IRQ level
rtx_type = <value>
use 0 - file interface, 1 - socket interface
rx_channel = <value>
DMA channel used for RX
tx_channel = <value>
DMA channel used for TX
rxfile = "<filename>"
filename, where to read data from
txfile = "<filename>"
filename, where to write data to
sockif = "<ifacename>"
interface name of ethernet socket
vapi_id = <hex_value>
VAPI id of this instance
*/
section ethernet
nethernets = 0
/*
device 0
baseaddr = 0x88000000
dma = 0
irq = 15
rtx_type = 0
tx_channel = 0
rx_channel = 1
rxfile = "/tmp/eth0.rx"
txfile = "/tmp/eth0.tx"
sockif = "lo"
enddevice
*/
end
/* GPIO SECTION
This section configure GPIOs
ngpios = <value>
make specified number of instances, configure each
instance within device - enddevice construct.
instance specific:
baseaddr = <hex_value>
address of first GPIO register for this device
irq = <value>
irq number for this device
base_vapi_id = <hex_value>
first VAPI id of this instance
GPIO uses 8 consecutive VAPI IDs
*/
section gpio
ngpios = 0
/*
device 0
baseaddr = 0xA0000000
irq = 23
base_vapi_id = 0x0200
enddevice
*/
end
/* VGA SECTION
This section configures VGA/LCD controller
nvgas = <value>
number of VGA devices connected
instance specific:
baseaddr = <hex_value>
address of first VGA register
irq = <value>
irq number for this device
refresh_rate = <value>
number of cycles between screen dumps
filename = "<filename>"
template name for generated names (e.g. "primary" produces "primary0023.bmp")
*/
section vga
nvgas = 0
/*
device 0
baseaddr = 0xb0000000
irq = 20
refresh_rate = 100000
filename = "primary"
enddevice
*/
end
/* FB SECTION
This section configures frame buffer
enabled = 0/1
whether frame buffer is enabled
baseaddr = <hex_value>
base address of frame buffer
paladdr = <hex_value>
base address of first palette entry
refresh_rate = <value>
number of cycles between screen dumps
filename = "<filename>"
template name for generated names (e.g. "primary" produces "primary0023.bmp")
*/
section fb
enabled = 0
baseaddr = 0xb8000000
refresh_rate = 100000
filename = "primary"
end
/* KBD SECTION
This section configures PS/2 compatible keyboard
enabled = 0/1
whether keyboard is enabled
baseaddr = <hex_value>
base address of the keyboard device
rxfile = "<filename>"
filename, where to read data from
*/
section kbd
enabled = 0
irq = 21
baseaddr = 0xb1000000
rxfile = "/tmp/kbd.rx"
end